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    Method for writing data to a semiconductor memory comprising a peripheral circuit section and a memory core section including a memory cell
    51.
    发明申请
    Method for writing data to a semiconductor memory comprising a peripheral circuit section and a memory core section including a memory cell 失效
    将数据写入半导体存储器的方法，所述半导体存储器包括外围电路部分和包括存储器单元的存储器核心部分

    公开(公告)号：US20050024932A1

    公开(公告)日：2005-02-03

    申请号：US10930591

    申请日：2004-08-31

    申请人： Shigeo Ohshima ,  Hiroyuki Ohtake ,  Katsumi Abe

    发明人： Shigeo Ohshima ,  Hiroyuki Ohtake ,  Katsumi Abe

    IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/00

    CPC分类号： G11C7/1069 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1096 ,  G11C11/4076 ,  G11C2207/107

    摘要： An input data register for latching write data is arranged in a position near a memory cell array of a memory core section. The input data register is arranged on the upstream side of a data path used for writing data into a memory cell. Write data input to a data pin which is arranged in the end position on the downstream side is latched in the input data register via a data input buffer, serial/parallel converting circuit and write data line. Data latched in the input data register is written into a memory cell via a DQ write driver, data line pair, I/O gate and bit line pair in a next write cycle.

    摘要翻译： 用于锁存写入数据的输入数据寄存器被布置在存储器芯部分的存储单元阵列附近的位置。 输入数据寄存器布置在用于将数据写入存储单元的数据路径的上游侧。 将写入数据引脚的数据输入写入到下游侧的终端位置，经由数据输入缓冲器，串行/并行转换电路和写数据线被锁存在输入数据寄存器中。 锁存在输入数据寄存器中的数据在下一个写周期中通过DQ写驱动器，数据线对，I / O门和位线对写入存储单元。

    Current-driven active matrix display panel for improved pixel programming
    52.
    发明申请
    Current-driven active matrix display panel for improved pixel programming 审中-公开
    电流驱动有源矩阵显示面板，用于改进像素编程

    公开(公告)号：US20050007361A1

    公开(公告)日：2005-01-13

    申请号：US10886615

    申请日：2004-07-09

    申请人： Katsuyuki Fujikura ,  Katsumi Abe ,  Masamichi Shimoda

    发明人： Katsuyuki Fujikura ,  Katsumi Abe ,  Masamichi Shimoda

    IPC分类号： H01L51/50 ,  G09G3/20 ,  G09G3/30 ,  G09G3/32 ,  G09G5/00

    CPC分类号： G09G3/325 ,  G09G2300/0852 ,  G09G2300/0861 ,  G09G2310/062

    摘要： A display device is comprised of a data line driver, a scan line driver, and a display panel. The display panel is composed of a plurality of drive legs disposed between a current output node and a first node having a fixed potential, each of the drive legs including a drive transistor having a source connected to the first node, a capacitor connected between a gate of the drive transistor and a second node having a fixed potential, a first switch connected between the current output node and a drain of the drive transistor, and a second switch connected between the gate and the drain of the drive transistor. The display panel further includes a data line, a third switch connected between the current output node and the data line, a current-driven element, a fourth switch connected between the current output node and the current-driven element.

    摘要翻译： 显示装置由数据线驱动器，扫描线驱动器和显示面板组成。 显示面板由设置在电流输出节点和具有固定电位的第一节点之间的多个驱动支路组成，每个驱动支路包括具有连接到第一节点的源极的驱动晶体管，连接在栅极之间的电容器 并且具有固定电位的第二节点，连接在电流输出节点和驱动晶体管的漏极之间的第一开关以及连接在驱动晶体管的栅极和漏极之间的第二开关。 显示面板还包括数据线，连接在当前输出节点和数据线之间的第三开关，电流驱动元件，连接在电流输出节点和电流驱动元件之间的第四开关。

    Multiport semiconductor memory device having RAM blocks and SAM blocks
    54.
    发明授权
    Multiport semiconductor memory device having RAM blocks and SAM blocks 失效
    具有RAM块和SAM块的多端口半导体存储器件

    公开(公告)号：US5319603A

    公开(公告)日：1994-06-07

    申请号：US778154

    申请日：1991-12-24

    申请人： Nobuo Watanabe ,  Koichi Magome ,  Katsumi Abe ,  Haruki Toda

    发明人： Nobuo Watanabe ,  Koichi Magome ,  Katsumi Abe ,  Haruki Toda

    IPC分类号： G11C7/10 ,  G11C8/00

    CPC分类号： G11C7/106 ,  G11C7/1051 ,  G11C7/1075 ,  G11C2207/107

    摘要： A multiport semiconductor memory device of this invention is constructed as having: a RAM having a first RAM unit and a second RAM unit; a SAM having a first SAM unit and a second SAM unit; and transfer circuit capable of selectively taking one of a split transfer state and a cross transfer state, in the split transfer state the first RAM unit and the first SAM unit being connected together and the second RAM unit and the second SAM unit being connected together, and in the cross transfer state the first RAM unit and the second SAM unit being connected together and the second RAM unit and the first SAM unit being connected together.

    摘要翻译： PCT No.PCT / JP91 / 00587第 371 1991年12月24日第 102（e）日期1991年12月24日PCT 1991年4月30日PCT PCT。 公开号WO91 / 17544 日本1991年11月14日。本发明的多端口半导体存储器件被构造为具有：具有第一RAM单元和第二RAM单元的RAM; 具有第一SAM单元和第二SAM单元的SAM; 以及转移电路，其能够选择性地采取分割转印状态和交叉转印状态之一，在分离转印状态下，第一RAM单元和第一SAM单元连接在一起，并且第二RAM单元和第二SAM单元连接在一起， 并且在交叉传送状态下，第一RAM单元和第二SAM单元连接在一起，并且第二RAM单元和第一SAM单元连接在一起。

    Thin-film transistor and method of manufacturing same
    55.
    发明授权
    Thin-film transistor and method of manufacturing same 有权
    薄膜晶体管及其制造方法

    公开(公告)号：US09153703B2

    公开(公告)日：2015-10-06

    申请号：US12527622

    申请日：2008-02-08

    申请人： Nobuyuki Kaji ,  Ryo Hayashi ,  Hisato Yabuta ,  Katsumi Abe

    发明人： Nobuyuki Kaji ,  Ryo Hayashi ,  Hisato Yabuta ,  Katsumi Abe

    IPC分类号： H01L21/336 ,  H01L29/786 ,  H01L29/10

    CPC分类号： H01L29/78696 ,  H01L29/105 ,  H01L29/7869

    摘要： There is provided a thin-film transistor including at least a substrate, a gate electrode, a gate insulating layer, an oxide semiconductor layer, a source electrode, a drain electrode and a protective layer, wherein the oxide semiconductor layer is an amorphous oxide containing at least one of the elements In, Ga and Zn, the gate electrode-side carrier density of the oxide semiconductor layer is higher than the protective layer-side carrier density thereof, and the film thickness of the oxide semiconductor layer is 30 nm±15 nm.

    摘要翻译： 提供了至少包括衬底，栅电极，栅极绝缘层，氧化物半导体层，源电极，漏电极和保护层的薄膜晶体管，其中氧化物半导体层是含有 元素In，Ga和Zn中的至少一种，氧化物半导体层的栅电极侧载流子密度高于其保护层侧载流子密度，氧化物半导体层的膜厚为30nm±15 nm。

    Drive circuit and drive method of light emitting display apparatus
    57.
    发明授权
    Drive circuit and drive method of light emitting display apparatus 有权
    发光显示装置的驱动电路及驱动方法

    公开(公告)号：US08610695B2

    公开(公告)日：2013-12-17

    申请号：US13086226

    申请日：2011-04-13

    申请人： Hisae Shimizu ,  Katsumi Abe

    发明人： Hisae Shimizu ,  Katsumi Abe

    IPC分类号： G09G5/00

    CPC分类号： G09G3/3233 ,  G09G3/3291 ,  G09G2300/0417 ,  G09G2300/043 ,  G09G2300/0819 ,  G09G2300/0861 ,  G09G2310/0262 ,  G09G2320/043

    摘要： A drive circuit for a light emitting display apparatus including a pixel circuit having a light emitting device for emitting a light having brightness determined based on supplied current and a drive transistor for supplying the current to the light emitting device, comprises a threshold value correction circuit converting a second signal including a threshold voltage of the drive transistor and a data voltage, the second signal being output from the drive transistor when a first signal including the data voltage is input into the control electrode of the drive transistor, into a third signal including the threshold voltage of an inverted polarity and the data voltage or a voltage corresponding to the data voltage, to output the converted third signal to the pixel circuit. The pixel circuit includes a switch for supplying the third signal to the control electrode of the drive transistor.

    摘要翻译： 一种用于发光显示装置的驱动电路，包括具有发光装置的像素电路，所述发光装置用于发射基于所提供的电流确定的亮度的光和用于向所述发光装置提供电流的驱动晶体管，所述驱动电路包括阈值校正电路转换 包括驱动晶体管的阈值电压的第二信号和数据电压，当包括数据电压的第一信号被输入到驱动晶体管的控制电极时，第二信号从驱动晶体管输出到第三信号，第三信号包括 反转极性的阈值电压和数据电压或对应于数据电压的电压，以将转换的第三信号输出到像素电路。 像素电路包括用于将第三信号提供给驱动晶体管的控制电极的开关。

    SEMICONDUCTOR MEMORY DEVICE
    58.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权
    半导体存储器件

    公开(公告)号：US20120250424A1

    公开(公告)日：2012-10-04

    申请号：US13432465

    申请日：2012-03-28

    申请人： Masahiro YOSHIHARA ,  Naofumi Abiko ,  Katsumi Abe

    发明人： Masahiro YOSHIHARA ,  Naofumi Abiko ,  Katsumi Abe

    IPC分类号： G11C7/06

    CPC分类号： G11C7/1006 ,  G11C7/106 ,  G11C7/1087 ,  G11C16/0483 ,  G11C16/26

    摘要： A sense amplifier circuit is connected to a bit-line and senses and amplifies a signal read from a memory cell. A first data latch is connected to a sense amplifier via a first bus. A second data latch is connected to a second bus. A plurality of circuit groups are repeatedly provided in a first direction, each circuit group comprising one sense amplifier circuit and one first data latch. The second data latch is provided between the circuit groups and an input/output buffer.

    摘要翻译： 感测放大器电路连接到位线，并感测并放大从存储单元读取的信号。 第一数据锁存器通过第一总线连接到读出放大器。 第二数据锁存器连接到第二总线。 在第一方向重复提供多个电路组，每个电路组包括一个读出放大器电路和一个第一数据锁存器。 第二数据锁存器设置在电路组和输入/输出缓冲器之间。

    Photoreceptor for electrophotography
    59.
    发明授权
    Photoreceptor for electrophotography 失效
    电子照相感光体

    公开(公告)号：US08247144B2

    公开(公告)日：2012-08-21

    申请号：US12524213

    申请日：2008-01-24

    申请人： Makoto Koike ,  Katsumi Abe ,  Atsushi Takesue

    发明人： Makoto Koike ,  Katsumi Abe ,  Atsushi Takesue

    IPC分类号： G03G5/06

    CPC分类号： G03G5/0614 ,  G03G5/0521 ,  G03G5/0607 ,  G03G5/0616 ,  G03G5/062

    摘要： An object of the invention is to provide a photoreceptor for electrophotography which has a low residual potential in an initial stage, is inhibited from increasing in residual potential, is prevented from decreasing in charge potential, and undergoes little fatigue deterioration even upon repeated use. The invention relates to a photoreceptor for electrophotography which has a photosensitive layer containing a cyclic phenol sulfide represented by the following general formula (1): and one or more charge-transporting agents each having an arylamino group in the molecule, and which has excellent durability.

    摘要翻译： 本发明的目的是提供一种用于电子照相的感光体，其在初始阶段具有低残留电位，被抑制增加残留电位，防止电荷电位降低，即使重复使用也几乎不会发生疲劳劣化。 本发明涉及一种电子照相用感光体，其具有含有下述通式（1）表示的环状苯酚硫化物的感光层和分子内各具有芳基氨基的一种或多种电荷输送剂，其耐久性优异 。