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    CURRENT FLATTENING CIRCUIT, CURRENT COMPENSATION CIRCUIT AND ASSOCIATED CONTROL METHOD
    51.
    发明申请
    CURRENT FLATTENING CIRCUIT, CURRENT COMPENSATION CIRCUIT AND ASSOCIATED CONTROL METHOD 审中-公开

    公开(公告)号：US20180224880A1

    公开(公告)日：2018-08-09

    申请号：US15427234

    申请日：2017-02-08

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Chun-Hsiung Hung ,  Shang-Chi Yang

    IPC: G05F5/00

    CPC classification number: G05F5/00

    Abstract: A current flattening circuit, a current compensation circuit and associated control method are provided. The current flattening circuit is electrically connected to a core node, and includes a reference voltage regulator and the current compensation circuit. The reference voltage regulator generates a reference voltage, wherein the reference voltage is constant. The current compensation circuit is electrically connected to the core node and the reference voltage regulator. The current compensation circuit generates a compensation current according to a potential difference between the reference voltage and a core voltage corresponding to the core node.

    NON-VOLATILE MEMORY WITH SECURITY KEY STORAGE
    53.
    发明申请
    NON-VOLATILE MEMORY WITH SECURITY KEY STORAGE 审中-公开

    公开(公告)号：US20180039581A1

    公开(公告)日：2018-02-08

    申请号：US15601582

    申请日：2017-05-22

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Ken-Hui Chen ,  Shih-Chang Huang

    IPC: G06F12/14 ,  H04L9/08 ,  G06F13/42

    Abstract: A system and method for utilizing a security key stored in non-volatile memory, and for generating a PUF-based data set on an integrated circuit including non-volatile memory cells, such as flash memory cells, are described. The method includes storing a security key in a particular block in a plurality of blocks of the non-volatile memory array; utilizing, in a security logic circuit coupled to the non-volatile memory array, the security key stored in the particular block in a protocol to enable access via a port by external devices or communication networks to data stored in blocks in the plurality of blocks; and enabling read-only access to the particular block by the security logic for use in the protocol, and preventing access to the particular block via the port.

    Method and apparatus for adjusting drain bias of a memory cell with addressed and neighbor bits
    57.
    发明授权
    Method and apparatus for adjusting drain bias of a memory cell with addressed and neighbor bits 有权
    用于调整具有寻址和相邻位的存储单元的漏极偏置的方法和装置

    公开(公告)号：US09396770B2

    公开(公告)日：2016-07-19

    申请号：US14833476

    申请日：2015-08-24

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Han-Sung Chen ,  Chung-Kuang Chen ,  Chun-Hsiung Hung

    IPC: G11C7/00 ,  G11C11/56 ,  G11C16/04 ,  G11C16/34

    CPC classification number: G11C7/00 ,  G11C11/5628 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/0458 ,  G11C16/3418 ,  G11C16/3427 ,  G11C2211/5621

    Abstract: The storage layer such as a nitride layer of a nonvolatile memory cell has two storage parts storing separately addressable data, typically respectively proximate to the source terminal and the drain terminal. The applied drain voltage while sensing the data of one of the storage parts depends on the data stored at the other storage part; the different parts can be in different, neighboring memory cells. If the data stored at the other storage part is represented by a threshold voltage exceeding a minimum threshold voltage, then the applied drain voltage is raised. This technology is useful in read operations and program verify operations to widen the threshold voltage window.

    Abstract translation: 诸如非易失性存储单元的氮化物层的存储层具有存储单独可寻址数据的两个存储部分，通常分别靠近源极端子和漏极端子。 感测一个存储部件的数据的施加的漏极电压取决于存储在另一个存储部分的数据; 不同的部分可以在不同的，相邻的存储单元中。 如果存储在另一个存储部分的数据由超过最小阈值电压的阈值电压表示，则所施加的漏极电压升高。 该技术在读取操作和程序验证操作中有助于拓宽阈值电压窗口。

    Method and apparatus for reduced read latency for consecutive read operations of memory of an integrated circuit
    58.
    发明授权
    Method and apparatus for reduced read latency for consecutive read operations of memory of an integrated circuit 有权
    用于集成电路的存储器的连续读取操作的用于减少读延迟的方法和装置

    公开(公告)号：US09281021B2

    公开(公告)日：2016-03-08

    申请号：US13854548

    申请日：2013-04-01

    Applicant: Macronix International Co., Ltd.

    Inventor： Chun-Hsiung Hung ,  Han Sung Chen ,  Ming Chao Lin

    IPC: G11C5/14 ,  G11C8/08 ,  G11C16/08 ,  G11C16/30

    CPC classification number: G11C7/22 ,  G11C5/145 ,  G11C8/08 ,  G11C16/08 ,  G11C16/30 ,  G11C2207/2272 ,  G11C2207/2281

    Abstract: An integrated circuit with memory can operate with reduced latency between consecutive operations such as read operations. At a first time, a first operation command is finished on a memory array on an integrated circuit. At a second time, a second operation command is begun on the memory array. A regulated output voltage from the charge pump is coupled to word lines in the memory array. From the first time to the second time, a regulated output voltage is maintained at about a word line operation voltage such as a read voltage.

    Abstract translation: 具有存储器的集成电路可以在诸如读取操作的连续操作之间以较低的延迟进行操作。 第一次，在集成电路上的存储器阵列上完成第一操作命令。 第二次，在存储器阵列上开始第二操作命令。 来自电荷泵的稳定的输出电压被耦合到存储器阵列中的字线。 从第一次到第二次，稳定的输出电压保持在诸如读取电压的字线操作电压。

    CIRCUIT FOR VOLTAGE DETECTION AND PROTECTION AND OPERATING METHOD THEREOF
    59.
    发明申请
    CIRCUIT FOR VOLTAGE DETECTION AND PROTECTION AND OPERATING METHOD THEREOF 有权
    用于电压检测和保护的电路及其操作方法

    公开(公告)号：US20160064921A1

    公开(公告)日：2016-03-03

    申请号：US14472520

    申请日：2014-08-29

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Yu-Meng Chaung ,  Chun-Hsiung Hung ,  Kuen-Long Chang ,  Ken-Hui Chen

    IPC: H02H3/20 ,  H02H3/24 ,  G11C5/14

    CPC classification number: H02H3/202 ,  G11C5/143 ,  H02H3/20 ,  H02H3/22 ,  H02H3/243 ,  H02H7/22

    Abstract: A circuit for voltage detection and protection comprises a first block, a first voltage detector, a second block and a second voltage detector. The first block receives a first voltage supply. The first voltage detector detects the first voltage supply and generates a first detecting signal when detecting the first voltage supply level is out of the first operating voltage range. The second block receives a second voltage supply. The second voltage detector detects the second voltage supply and generates a second detecting signal when detecting the second voltage supply level is out of the second operating voltage range. The first block performs a protection operation on the circuit when monitoring at least one of the first and second detecting signals.

    Abstract translation: 用于电压检测和保护的电路包括第一块，第一电压检测器，第二块和第二电压检测器。 第一块接收第一个电压源。 第一电压检测器检测第一电压源，并且当检测到第一电压供应电平在第一工作电压范围之外时产生第一检测信号。 第二块接收第二电压源。 第二电压检测器检测第二电压源，并且当检测到第二电压供应电平在第二工作电压范围之外时产生第二检测信号。 当监视第一和第二检测信号中的至少一个时，第一块在电路上执行保护操作。

    STABILIZATION OF OUTPUT TIMING DELAY
    60.
    发明申请
    STABILIZATION OF OUTPUT TIMING DELAY 有权
    输出时序延迟稳定

    公开(公告)号：US20160049925A1

    公开(公告)日：2016-02-18

    申请号：US14458936

    申请日：2014-08-13

    Applicant: Macronix International Co., Ltd.

    Inventor： Yu-Meng Chaung ,  Chun-Hsiung Hung ,  Kuen-Long Chang ,  Ken-Hui Chen

    IPC: H03K3/011 ,  H03K3/012

    CPC classification number: H03K19/018521 ,  H03K19/00384

    Abstract: An integrated circuit includes an output buffer and a control circuit. The output buffer has a signal input, a signal output, and a set of control inputs. The output buffer has an output buffer delay, and a driving strength adjustable in response to control signals applied to the set of control inputs. Alternatively, the output buffer delay is variable. The control circuit is connected to the set of control inputs of the output buffer. The control circuit uses first and second timing signals to generate the control signals, and can include a first delay circuit that generates the first timing signal with a first delay, and a second delay circuit that generates the second timing signal with a second delay that correlates with the output buffer delay.

    Abstract translation: 集成电路包括输出缓冲器和控制电路。 输出缓冲器具有信号输入，信号输出和一组控制输入。 输出缓冲器具有输出缓冲器延迟，并且响应于施加到该组控制输入的控制信号而可调整驱动强度。 或者，输出缓冲器延迟是可变的。 控制电路连接到输出缓冲器的一组控制输入。 控制电路使用第一和第二定时信号来产生控制信号，并且可以包括产生具有第一延迟的第一定时信号的第一延迟电路和产生具有第二延迟的第二定时信号的第二延迟电路， 与输出缓冲区延迟。

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