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    Surface proteins from gram-positive bacteria having highly conserved motifs and antibodies that recognize them
    52.
    发明申请
    Surface proteins from gram-positive bacteria having highly conserved motifs and antibodies that recognize them 失效
    来自具有高度保守基序的革兰氏阳性细菌的表面蛋白和识别它们的抗体

    公开(公告)号：US20050002925A1

    公开(公告)日：2005-01-06

    申请号：US10911507

    申请日：2004-08-05

    申请人： Yi Xu ,  Magnus Hook

    发明人： Yi Xu ,  Magnus Hook

    IPC分类号： A61K39/00 ,  C07K14/31 ,  C07K14/315 ,  C07K16/12 ,  A61K39/395

    CPC分类号： C07K14/3156 ,  A61K39/00 ,  A61K2039/505 ,  C07K14/31 ,  C07K14/315 ,  C07K16/1267 ,  Y10S930/29

    摘要： Isolated peptide sequences and proteins containing these sequences are provided which are useful in the prevention and treatment of infection caused by Gram-positive bacteria. The peptide sequences have been shown to be highly conserved motifs in the surface proteins of Gram-positive bacteria, and these consensus sequences include amino acid sequences such as LPXTG (SEQ ID NO:13), ALKTGKIDIIISGMTSTPERKK (SEQ ID NO:14), VEGAVVEKPVAEAYLKQN (SEQ ID NO:15), and EYAGVDIDLAKKIAK (SEQ ID NO:16). By virtue of the highly conserved regions, the sequences and the proteins including these sequences can be utilized to generate antibodies which can recognize these highly conserved motifs and the proteins containing them and thus be useful in the treatment or prevention of a wide range of infections caused by Gram-positive bacteria.

    摘要翻译： 提供了含有这些序列的分离的肽序列和蛋白质，其可用于预防和治疗由革兰氏阳性菌引起的感染。 已经显示肽序列在革兰氏阳性细菌的表面蛋白中是高度保守的基序，并且这些共有序列包括氨基酸序列，例如LPXTG（SEQ ID NO：13），ALKTGKIDIIISGMTSTPERKK（SEQ ID NO：14），VEGAVVEKPVAEAYLKQN （SEQ ID NO：15）和EYAGVDIDLAKKIAK（SEQ ID NO：16）。 由于高度保守的区域，包括这些序列的序列和蛋白质可用于产生能识别这些高度保守的基序和含有它们的蛋白质的抗体，因此可用于治疗或预防引起的广泛感染 通过革兰氏阳性菌。

    Method for cleaning semiconductor structures using hydrocarbon and solvents in a repetitive vapor phase/liquid phase sequence
    54.
    发明授权
    Method for cleaning semiconductor structures using hydrocarbon and solvents in a repetitive vapor phase/liquid phase sequence 失效
    在重复气相/液相序列中使用烃和溶剂清洗半导体结构的方法

    公开(公告)号：US06692579B2

    公开(公告)日：2004-02-17

    申请号：US09764244

    申请日：2001-01-19

    申请人： Sudipto Ranendra Roy ,  Yi Xu ,  Simon Chooi ,  Yakub Aliyu ,  Mei Sheng Zhou ,  John Leonard Sudijono ,  Paul Kwok Keung Ho ,  Subhash Gupta

    发明人： Sudipto Ranendra Roy ,  Yi Xu ,  Simon Chooi ,  Yakub Aliyu ,  Mei Sheng Zhou ,  John Leonard Sudijono ,  Paul Kwok Keung Ho ,  Subhash Gupta

    IPC分类号： B08B300

    CPC分类号： H01L21/02057 ,  B08B3/00 ,  C11D7/24 ,  C11D7/5027 ,  C11D11/0047 ,  H01L21/02063 ,  H01L21/6704

    摘要： A method for cleaning a semiconductor structure using vapor phase condensation with a thermally vaporized cleaning agent, a hydrocarbon vaporized by pressure variation, or a combination of the two. In the thermally vaporized cleaning agent process, a semiconductor structure is lowered into a vapor blanket in a thermal gradient cleaning chamber at atmospheric pressure formed by heating a liquid cleaning agent below the vapor blanket and cooling the liquid cleaning agent above the vapor blanket causing it to condense and return to the bottom of the thermal gradient cleaning chamber. The semiconductor structure is then raised above the vapor blanket and the cleaning agent condenses on all of the surfaces of the semiconductor structure removing contaminants and is returned to the bottom of the chamber by gravity. In the pressurized hydrocarbon process, a semiconductor structure is placed into a variable pressure cleaning chamber, having a piston which changes the pressure by reducing or increasing the volume of the chamber. The semiconductor structure first exposed to the hydrocarbon in vapor phase, then the piston is lowered to condense the hydrocarbon. A semiconductor structure can be cleaned by either or both of these processes by repetitive vaporization/condensation cycles.

    摘要翻译： 一种使用与气相清洗剂进行气相冷凝的半导体结构，通过压力变化蒸发的烃或两者的组合来清洗半导体结构的方法。 在热蒸发清洗剂方法中，半导体结构在大气压力的热梯度清洗室内被降低成蒸气层，所述热梯度清洗室通过将蒸气层下方的液体清洗剂加热而形成，并将该液体清洁剂冷却至蒸气层以上 冷凝并返回到热梯度清洗室的底部。 然后将半导体结构升高到蒸气层上方，并且清洁剂在半导体结构的所有表面上冷凝除去杂质，并通过重力返回到室的底部。 在加压烃工艺中，将半导体结构放置在可变压力清洁室中，其具有通过减小或增加室的体积来改变压力的活塞。 半导体结构首先暴露于气相中的烃，然后降低活塞以使烃冷凝。 半导体结构可以通过这些过程中的任一个或两者通过重复的蒸发/冷凝循环进行清洁。

    Air bridge process for forming air gaps
    57.
    发明授权
    Air bridge process for forming air gaps 有权
    用于形成气隙的气桥过程

    公开(公告)号：US06265321B1

    公开(公告)日：2001-07-24

    申请号：US09550264

    申请日：2000-04-17

    申请人： Simon Chooi ,  Mei-Sheng Zhou ,  Yi Xu

    发明人： Simon Chooi ,  Mei-Sheng Zhou ,  Yi Xu

    IPC分类号： H01L2100

    CPC分类号： H01L21/7682 ,  H01L21/76807

    摘要： A method for reducing RC delay in integrated circuits by lowering the dielectric constant of the intermetal dielectric material between metal interconnects or metal damascene interconnects is described. The dielectric constant of the intermetal dielectric is lowered by introducing air into the intermetal dielectric between metal interconnections. An air bridge comprising a porous material, preferably amorphous silicon, porous silicon oxide, or porous silsesquioxane, is deposited over a layer containing a reactive organic material. An oxygen plasma treatment or an anisotropic etching through the pores in the air bridge layer removes at least a portion of the reactive material, leaving air plugs within the intermetal dielectric.

    摘要翻译： 描述了通过降低金属互连或金属镶嵌互连之间的金属间电介质材料的介电常数来减小集成电路中的RC延迟的方法。 通过在金属互连之间的金属间电介质中引入空气来降低金属间电介质的介电常数。 包括多孔材料，优选非晶硅，多孔氧化硅或多孔倍半硅氧烷的空气桥被沉积在含有反应性有机材料的层上。 通过空气桥接层中的孔的氧等离子体处理或各向异性蚀刻去除至少一部分反应性材料，从而将空气塞留在金属间电介质内。

    Method of fabrication of anti-fuse integrated with dual damascene process
    59.
    发明授权
    Method of fabrication of anti-fuse integrated with dual damascene process 有权
    与双镶嵌工艺集成的抗熔丝的制造方法

    公开(公告)号：US6124194A

    公开(公告)日：2000-09-26

    申请号：US439365

    申请日：1999-11-15

    申请人： Kai Shao ,  Yi Xu ,  Cerdin Lee ,  Shao-Fu Sanford Chu

    发明人： Kai Shao ,  Yi Xu ,  Cerdin Lee ,  Shao-Fu Sanford Chu

    IPC分类号： H01L21/768 ,  H01L23/525 ,  H07L29/00

    CPC分类号： H01L21/7681 ,  H01L23/5252 ,  H01L2924/0002

    摘要： A method of fabricating an anti-fuse module and dual damascene interconnect structure comprises the following steps. A semiconductor structure having at least two exposed metal lines covered by a first dielectric layer is provided. A first metal line is within an anti-fuse area and a second metal line is within an interconnect area. A first metal via is formed within the first dielectric layer within the anti-fuse area with the first metal via contacting the first metal line. A SiN layer is deposited over the first dielectric layer and the first metal via. The SiN layer is patterned to form at least two openings. A first opening exposes the first metal via, and a second opening exposes a portion of the first dielectric layer above the second metal line. A fusing element layer is deposited and patterned over the patterned SiN layered structure to form a fusing element over the first metal via. Simultaneously, an anti-fuse metal line is formed over the fusing element to form an anti-fuse module within the anti-fuse area, and a dual damascene interconnect is formed over, and contacting with, the second metal line and within the interconnect area.

    摘要翻译： 一种制造抗熔丝模块和双镶嵌互连结构的方法包括以下步骤。 提供具有被第一介电层覆盖的至少两个暴露的金属线的半导体结构。 第一金属线在反熔丝区内，第二金属线在互连区内。 第一金属通孔形成在反熔丝区域内的第一电介质层内，第一金属通孔接触第一金属线。 在第一介电层和第一金属通孔上沉积SiN层。 图案化SiN层以形成至少两个开口。 第一开口暴露第一金属通孔，第二开口暴露第二电介质层的第二金属线上方的一部分。 在图案化的SiN层状结构上沉积并图案化定影元件层，以在第一金属通孔之上形成定影元件。 同时，在熔断元件上方形成抗熔丝金属线，以在反熔丝区域内形成反熔丝模块，并且在第二金属线之间和互连区内形成双面镶嵌互连 。