公开(公告)号：US20160056038A1

公开(公告)日：2016-02-25

申请号：US14929070

申请日：2015-10-30

Applicant: Micron Technology, Inc.

Inventor： Nik Mirin ,  Tsai-Yu Huang ,  Vishwanath Bhat ,  Chris M. Carlson ,  Vassil N. Antonov

IPC: H01L21/02 ,  H01L23/367 ,  H01L49/02 ,  H01L21/3205 ,  H01L27/108 ,  H01L23/373 ,  H01L21/285

CPC classification number: H01L21/02186 ,  C01G23/04 ,  C23C16/405 ,  C23C16/45534 ,  H01G4/085 ,  H01G4/1227 ,  H01G4/33 ,  H01L21/02233 ,  H01L21/02244 ,  H01L21/28556 ,  H01L21/32051 ,  H01L23/367 ,  H01L23/3735 ,  H01L23/3736 ,  H01L27/10808 ,  H01L27/1085 ,  H01L27/10852 ,  H01L28/40 ,  H01L28/60 ,  H01L2924/0002 ,  H05K1/0203 ,  Y10T428/24802 ,  Y10T428/24975 ,  H01L2924/00

Abstract: Some embodiments include methods of forming rutile-type titanium oxide. A monolayer of titanium nitride may be formed. The monolayer of titanium nitride may then be oxidized at a temperature less than or equal to about 550° C. to convert it into a monolayer of rutile-type titanium oxide. Some embodiments include methods of forming capacitors that have rutile-type titanium oxide dielectric, and that have at least one electrode comprising titanium nitride. Some embodiments include thermally conductive stacks that contain titanium nitride and rutile-type titanium oxide, and some embodiments include methods of forming such stacks.

Abstract translation: 一些实施方案包括形成金红石型氧化钛的方法。 可以形成单层的氮化钛。 氮化钛单层然后可以在小于或等于约550℃的温度下被氧化，以将其转化为金红石型氧化钛的单层。 一些实施方案包括形成具有金红石型氧化钛电介质的电容器并且具有至少一个包含氮化钛的电极的方法。 一些实施方案包括含有氮化钛和金红石型氧化钛的导热叠层，并且一些实施方案包括形成这种叠层的方法。

公开(公告)号：US09209013B2

公开(公告)日：2015-12-08

申请号：US13956211

申请日：2013-07-31

Applicant: Micron Technology, Inc.

Inventor： Nik Mirin ,  Tsai-Yu Huang ,  Vishwanath Bhat ,  Chris M. Carlson ,  Vassil N. Antonov

IPC: H01L21/02 ,  C23C16/40 ,  C23C16/455 ,  H01G4/08 ,  H01G4/12 ,  H01G4/33 ,  H01L27/108 ,  H01L49/02 ,  C01G23/04 ,  H01L23/373 ,  H05K1/02

CPC classification number: H01L21/02186 ,  C01G23/04 ,  C23C16/405 ,  C23C16/45534 ,  H01G4/085 ,  H01G4/1227 ,  H01G4/33 ,  H01L21/02233 ,  H01L21/02244 ,  H01L21/28556 ,  H01L21/32051 ,  H01L23/367 ,  H01L23/3735 ,  H01L23/3736 ,  H01L27/10808 ,  H01L27/1085 ,  H01L27/10852 ,  H01L28/40 ,  H01L28/60 ,  H01L2924/0002 ,  H05K1/0203 ,  Y10T428/24802 ,  Y10T428/24975 ,  H01L2924/00

Abstract: Some embodiments include methods of forming rutile-type titanium oxide. A monolayer of titanium nitride may be formed. The monolayer of titanium nitride may then be oxidized at a temperature less than or equal to about 550° C. to convert it into a monolayer of rutile-type titanium oxide. Some embodiments include methods of forming capacitors that have rutile-type titanium oxide dielectric, and that have at least one electrode comprising titanium nitride. Some embodiments include thermally conductive stacks that contain titanium nitride and rutile-type titanium oxide, and some embodiments include methods of forming such stacks.

Abstract translation: 一些实施方案包括形成金红石型氧化钛的方法。 可以形成单层的氮化钛。 然后氮化钛单层可以在小于或等于约550℃的温度下被氧化，以将其转化为金红石型氧化钛的单层。 一些实施方案包括形成具有金红石型氧化钛电介质的电容器并且具有至少一个包含氮化钛的电极的方法。 一些实施方案包括含有氮化钛和金红石型氧化钛的导热叠层，并且一些实施方案包括形成这种叠层的方法。

公开(公告)号：US20130280426A1

公开(公告)日：2013-10-24

申请号：US13926289

申请日：2013-06-25

Applicant: Micron Technology, Inc.

Inventor： Zhe Song ,  Chris M. Carlson

IPC: C23C16/455

CPC classification number: C23C16/45553 ,  C23C16/405 ,  C23C16/45527 ,  H01G4/085 ,  H01G4/12 ,  H01G4/33 ,  H01L21/02159 ,  H01L21/02178 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/0228 ,  H01L28/40

Abstract: A method of forming a material over a substrate includes performing at least one iteration of the following temporally separated ALD-type sequence. First, an outermost surface of a substrate is contacted with a first precursor to chemisorb a first species onto the outermost surface from the first precursor. Second, the outermost surface is contacted with a second precursor to chemisorb a second species different from the first species onto the outermost surface from the second precursor. The first and second precursors include ligands and different central atoms. At least one of the first and second precursors includes at least two different composition ligands. The two different composition ligands are polyatomic or a lone halogen. Third, the chemisorbed first species and the chemisorbed second species are contacted with a reactant which reacts with the first species and with the second species to form a reaction product new outermost surface of the substrate.

Abstract translation: 在衬底上形成材料的方法包括进行以下时间上分离的ALD型序列的至少一次迭代。 首先，将基底的最外表面与第一前体接触，以将第一种类化学吸附到来自第一前体的最外表面上。 第二，最外面的表面与第二前体接触，以将与第一种不同的第二物种化学吸附到与第二前体的最外表面上。 第一和第二前体包括配体和不同的中心原子。 第一和第二前体中的至少一种前体包括至少两种不同的组成配体。 两种不同的组成配体是多原子或单卤素。 第三，化学吸附的第一物质和化学吸附的第二物质与反应物接触，所述反应物与第一物质和第二物质反应以形成反应产物基底的新的最外表面。

公开(公告)号：US20240284675A1

公开(公告)日：2024-08-22

申请号：US18649366

申请日：2024-04-29

Applicant: Micron Technology, Inc.

Inventor： Albert Fayrushin ,  Haitao Liu ,  Chris M. Carlson

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

Abstract: A microelectronic device includes a stack structure comprising a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. At least one pillar, comprising a channel material, extends through the stack structure. A source region, below the stack structure, comprises a doped material. A vertical extension of the doped material protrudes upward to an interface with the channel material at elevation within the stack structure (e.g., an elevation proximate or laterally overlapping in elevation at least one source-side GIDL region). The microelectronic device structure may be formed by a method that includes forming a lateral opening through cell materials of the pillar, recessing the channel material to form a vertical recess, and forming the doped material in the vertical recess. Additional microelectronic devices are also disclosed, as are related methods and electronic systems.

公开(公告)号：US11974430B2

公开(公告)日：2024-04-30

申请号：US17158859

申请日：2021-01-26

Applicant: Micron Technology, Inc.

Inventor： Albert Fayrushin ,  Haitao Liu ,  Chris M. Carlson

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

Abstract: A microelectronic device includes a stack structure comprising a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. At least one pillar, comprising a channel material, extends through the stack structure. A source region, below the stack structure, comprises a doped material. A vertical extension of the doped material protrudes upward to an interface with the channel material at elevation within the stack structure (e.g., an elevation proximate or laterally overlapping in elevation at least one source-side GIDL region). The microelectronic device structure may be formed by a method that includes forming a lateral opening through cell materials of the pillar, recessing the channel material to form a vertical recess, and forming the doped material in the vertical recess. Additional microelectronic devices are also disclosed, as are related methods and electronic systems.

公开(公告)号：US11943924B2

公开(公告)日：2024-03-26

申请号：US17181901

申请日：2021-02-22

Applicant: Micron Technology, Inc.

Inventor： Chris M. Carlson

IPC: H01L21/28 ,  H01L29/423 ,  H01L29/51 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L29/40117 ,  H01L29/4234 ,  H01L29/512 ,  H10B43/35

Abstract: Various embodiments include methods and apparatus having a number of charge trap structures, where each charge trap structure includes a dielectric barrier between a gate and a blocking dielectric region, the blocking dielectric region located on a charge trap region of the charge trap structure. At least a portion of the gate can be separated by a void from a region which the charge trap structure is directly disposed. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US11751393B2

公开(公告)日：2023-09-05

申请号：US17524987

申请日：2021-11-12

Applicant: Micron Technology, Inc.

Inventor： Manzar Siddik ,  Chris M. Carlson ,  Terry H. Kim ,  Kunal Shrotri ,  Srinath Venkatesan

IPC: H01L27/11582 ,  H10B43/27 ,  H01L21/3215 ,  H01L21/3115 ,  H10B41/27

CPC classification number: H10B43/27 ,  H01L21/3115 ,  H01L21/3215 ,  H10B41/27

Abstract: A memory array comprising strings of memory cells comprises a vertical stack comprising alternating insulative tiers and conductive tiers. The strings of memory cells in the stack comprise channel-material strings and storage-material strings extending through the insulative tiers and the conductive tiers. At least some of the storage material of the storage-material strings in individual of the insulative tiers are intrinsically less charge-transmissive than is the storage material in the storage-material strings in individual of the conductive tiers. Other aspects, including method, are disclosed.

公开(公告)号：US11672118B2

公开(公告)日：2023-06-06

申请号：US17013047

申请日：2020-09-04

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  Richard J. Hill ,  Gurtej S. Sandhu ,  Byeung Chul Kim ,  Francois H. Fabreguette ,  Chris M. Carlson ,  Michael E. Koltonski ,  Shane J. Trapp

IPC: H01L27/11582

CPC classification number: H01L27/11582

Abstract: An electronic device comprising a cell region comprising stacks of alternating dielectric materials and conductive materials. A pillar region is adjacent to the cell region and comprises storage node segments adjacent to adjoining oxide materials and adjacent to a tunnel region. The storage node segments are separated by a vertical portion of the tunnel region. A high-k dielectric material is adjacent to the conductive materials of the cell region and to the adjoining oxide materials of the pillar region. Additional electronic devices are disclosed, as are methods of forming an electronic device and related systems.

公开(公告)号：US11641742B2

公开(公告)日：2023-05-02

申请号：US17468170

申请日：2021-09-07

Applicant: Micron Technology, Inc.

Inventor： Cole Smith ,  Ramey M. Abdelrahaman ,  Silvia Borsari ,  Chris M. Carlson ,  David Daycock ,  Matthew J. King ,  Jin Lu

IPC: H01L27/11582 ,  G11C5/06 ,  H01L27/11556 ,  H01L27/1157 ,  H01L23/522 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/11519

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. Horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. A wall is formed in individual of the trenches laterally-between immediately-laterally-adjacent of the memory-block regions. The forming of the wall comprises lining sides of the trenches with insulative material comprising at least one of an insulative nitride and elemental-form boron. A core material is formed in the trenches to span laterally-between the at least one of the insulative nitride and the elemental-form boron. Structure independent of method is disclosed.

公开(公告)号：US20220077186A1

公开(公告)日：2022-03-10

申请号：US17524987

申请日：2021-11-12

Applicant: Micron Technology, Inc.

Inventor： Manzar Siddik ,  Chris M. Carlson ,  Terry H. Kim ,  Kunal Shrotri ,  Srinath Venkatesan

IPC: H01L27/11582 ,  H01L21/3215 ,  H01L21/3115 ,  H01L27/11556

Abstract: A memory array comprising strings of memory cells comprises a vertical stack comprising alternating insulative tiers and conductive tiers. The strings of memory cells in the stack comprise channel-material strings and storage-material strings extending through the insulative tiers and the conductive tiers. At least some of the storage material of the storage-material strings in individual of the insulative tiers are intrinsically less charge-transmissive than is the storage material in the storage-material strings in individual of the conductive tiers. Other aspects, including method, are disclosed.