公开(公告)号：US07402883B2

公开(公告)日：2008-07-22

申请号：US11380074

申请日：2006-04-25

申请人： Chih-Chao Yang ,  Shyng-Tsong Chen ,  Shom Ponoth ,  Terry A. Spooner

发明人： Chih-Chao Yang ,  Shyng-Tsong Chen ,  Shom Ponoth ,  Terry A. Spooner

IPC分类号： H01L23/48

CPC分类号： H01L21/76846 ,  H01L21/76865

摘要： A back end of the line (BEOL) structure of a semiconductor device is presented. In one embodiment, the structure may include a first liner layer disposed on an intermediate interconnect structure, the intermediate interconnect structure having an opening disposed between two surfaces of a dielectric material, wherein the first liner layer is in direct contact with at least a portion of a conductive wiring material of an underneath interconnect layer; a noble metal layer disposed on the first liner layer at least in the opening; and a conductive wiring material disposed on the noble metal layer, the conductive wiring material substantially filling the opening; wherein the first liner layer, the noble metal layer and the conductive wiring material are coplanar with the two surfaces of the dielectric material of the intermediate interconnect structure, and the noble metal layer includes a different material than the first liner layer.

摘要翻译： 提出了半导体器件的线路（BEOL）结构的后端。 在一个实施例中，该结构可以包括设置在中间互连结构上的第一衬里层，所述中间互连结构具有设置在电介质材料的两个表面之间的开口，其中第一衬垫层与至少一部分 下面的互连层的导电布线材料; 至少在所述开口中设置在所述第一衬垫层上的贵金属层; 以及布置在所述贵金属层上的导电布线材料，所述导电布线材料基本上填充所述开口; 其中所述第一衬里层，所述贵金属层和所述导电布线材料与所述中间互连结构的介电材料的两个表面共面，并且所述贵金属层包括与所述第一衬里层不同的材料。

公开(公告)号：US20070048981A1

公开(公告)日：2007-03-01

申请号：US11162219

申请日：2005-09-01

申请人： Griselda Bonilla ,  Richard Conti ,  Timothy Dalton ,  Nicholas Fuller ,  Kelly Malone ,  Satyanarayana Nitta ,  Shom Ponoth

发明人： Griselda Bonilla ,  Richard Conti ,  Timothy Dalton ,  Nicholas Fuller ,  Kelly Malone ,  Satyanarayana Nitta ,  Shom Ponoth

IPC分类号： H01L21/04

CPC分类号： H01L21/31695 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02304 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/76826

摘要： A method for protecting a semiconductor device from carbon depletion type damage includes enriching an exposed surface of a porous interlevel dielectric material (ILD) with a carbon based material, and implementing a plasma based operation on the porous ILD material. The enriching of the porous ILD material reduces effects of carbon depletion as a result of the plasma based operation.

摘要翻译： 用于保护半导体器件免受碳耗竭型损伤的方法包括用碳基材料富集多孔层间电介质材料（ILD）的暴露表面，以及对多孔ILD材料实施基于等离子体的操作。 作为基于等离子体的操作的结果，多孔ILD材料的富集减少了碳耗竭的影响。

公开(公告)号：US09263391B2

公开(公告)日：2016-02-16

申请号：US13089958

申请日：2011-04-19

申请人： Satya V. Nitta ,  Shom Ponoth

发明人： Satya V. Nitta ,  Shom Ponoth

IPC分类号： H01L23/52 ,  H01L23/532 ,  H01L23/48 ,  H01L23/522 ,  H01L21/768

CPC分类号： H01L21/76807 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/48 ,  H01L23/481 ,  H01L23/52 ,  H01L23/522 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

摘要： A dual damascene article of manufacture comprises a trench containing a conductive metal column where the trench and the conductive metal column extend down into and are contiguous with a via. The trench and the conductive metal column and the via have a common axis. These articles comprise interconnect structures incorporating air-gap spacers containing metal/insulator structures for Very Large Scale Integrated (VLSI) and Ultra Large Scale Integrated (ULSI) devices and packaging. The trench in this regard comprises a sidewall air-gap immediately adjacent the side walls of the trench and the conductive metal column, the sidewall air-gap extending down to the via to a depth below a line fixed by the bottom of the trench, and continues downward in the via for a distance of from about 1 Angstrom below the line to the full depth of the via. In another aspect, the article of manufacture comprises a capped dual damascene structure.

公开(公告)号：US09041116B2

公开(公告)日：2015-05-26

申请号：US13478154

申请日：2012-05-23

申请人： Bruce B. Doris ,  Kangguo Cheng ,  Steven J. Holmes ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Shom Ponoth ,  Raghavasimhan Sreenivasan ,  Stefan Schmitz

发明人： Bruce B. Doris ,  Kangguo Cheng ,  Steven J. Holmes ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Shom Ponoth ,  Raghavasimhan Sreenivasan ,  Stefan Schmitz

IPC分类号： H01L27/092 ,  H01L27/12 ,  H01L21/8238

CPC分类号： H01L21/823835 ,  H01L21/823842

摘要： A method for forming an electrical device that includes forming a high-k gate dielectric layer over a semiconductor substrate that is patterned to separate a first portion of the high-k gate dielectric layer that is present on a first conductivity device region from a second portion of the high-k gate dielectric layer that is present on a second conductivity device region. A connecting gate conductor is formed on the first portion and the second portion of the high-k gate dielectric layer. The connecting gate conductor extends from the first conductivity device region over the isolation region to the second conductivity device region. One of the first conductivity device region and the second conductivity device region may then be exposed to an oxygen containing atmosphere. Exposure with the oxygen containing atmosphere modifies a threshold voltage of the semiconductor device that is exposed.

公开(公告)号：US08932918B2

公开(公告)日：2015-01-13

申请号：US13598080

申请日：2012-08-29

申请人： Kangguo Cheng ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

发明人： Kangguo Cheng ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

IPC分类号： H01L21/338

CPC分类号： H01L29/7851 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66803 ,  H01L29/7848 ,  H01L29/7849

摘要： A finFET with self-aligned punchthrough stopper and methods of manufacture are disclosed. The method includes forming spacers on sidewalls of a gate structure and fin structures of a finFET device. The method further includes forming a punchthrough stopper on exposed sidewalls of the fin structures, below the spacers. The method further includes diffusing dopants from the punchthrough stopper into the fin structures. The method further includes forming source and drain regions adjacent to the gate structure and fin structures.

摘要翻译： 公开了具有自对准穿通塞子的finFET和制造方法。 该方法包括在栅极结构的侧壁和finFET器件的翅片结构上形成间隔物。 该方法还包括在隔片的下方在翅片结构的暴露的侧壁上形成穿通止动件。 该方法还包括将穿透止动器的掺杂剂扩散到鳍结构中。 该方法还包括形成与栅极结构和鳍结构相邻的源区和漏区。

公开(公告)号：US08853076B2

公开(公告)日：2014-10-07

申请号：US13607856

申请日：2012-09-10

申请人： Su Chen Fan ,  David V. Horak ,  Shom Ponoth ,  David L. Rath ,  Muthumanickam Sankarapandian

发明人： Su Chen Fan ,  David V. Horak ,  Shom Ponoth ,  David L. Rath ,  Muthumanickam Sankarapandian

IPC分类号： H01L21/44

CPC分类号： H01L21/28088 ,  H01L21/76897 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

摘要： Self-aligned contacts in a metal gate structure and methods of manufacture are disclosed herein. The method includes forming a metal gate structure having a sidewall structure. The method further includes recessing the metal gate structure and forming a masking material within the recess. The method further includes forming a borderless contact adjacent to the metal gate structure, overlapping the masking material and the sidewall structure.

摘要翻译： 本文公开了金属栅极结构中的自对准触点和制造方法。 该方法包括形成具有侧壁结构的金属栅极结构。 该方法还包括使金属栅极结构凹陷并在凹槽内形成掩模材料。 该方法还包括在金属栅极结构附近形成无边界接触，与掩模材料和侧壁结构重叠。

公开(公告)号：US08772874B2

公开(公告)日：2014-07-08

申请号：US13216554

申请日：2011-08-24

申请人： Kangguo Cheng ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

发明人： Kangguo Cheng ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392

CPC分类号： H01L29/66477 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/823418 ,  H01L21/84 ,  H01L29/66045 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66659 ,  H01L29/66803 ,  H01L29/785

摘要： At least one drain-side surfaces of a field effect transistor (FET) structure, which can be a structure for a planar FET or a fin FET, is structurally damaged by an angled ion implantation of inert or electrically active dopants, while at least one source-side surface of the transistor is protected from implantation by a gate stack and a gate spacer. Epitaxial growth of a semiconductor material is retarded on the at least one structurally damaged drain-side surface, while epitaxial growth proceeds without retardation on the at least one source-side surface. A raised epitaxial source region has a greater thickness than a raised epitaxial drain region, thereby providing an asymmetric FET having lesser source-side external resistance than drain-side external resistance, and having lesser drain-side overlap capacitance than source-side overlap capacitance.

摘要翻译： 作为平面FET或鳍式FET的结构的场效应晶体管（FET）结构的至少一个漏极侧表面在结构上被惰性或电活性掺杂剂的成角度的离子注入损坏，而至少一个 保护晶体管的源极侧表面不被栅极堆叠和栅极间隔物的注入。 半导体材料的外延生长在至少一个结构损坏的漏极侧表面上延迟，而外延生长在至少一个源极侧表面上没有延迟。 凸起的外延源区域具有比凸起的外延漏极区域更大的厚度，从而提供具有比漏极侧外部电阻更小的源极侧外部电阻并且具有比源极重叠电容更少的漏极侧重叠电容的非对称FET。

公开(公告)号：US08703550B2

公开(公告)日：2014-04-22

申请号：US13525642

申请日：2012-06-18

申请人： Bruce B. Doris ,  Shom Ponoth ,  Prasanna Khare ,  Qing Liu ,  Nicolas Loubet ,  Maud Vinet

发明人： Bruce B. Doris ,  Shom Ponoth ,  Prasanna Khare ,  Qing Liu ,  Nicolas Loubet ,  Maud Vinet

IPC分类号： H01L21/00 ,  H01L21/84

CPC分类号： H01L21/76879 ,  H01L21/0217 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76897 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/66628 ,  H01L29/78609

摘要： A shallow trench is formed to extend into a handle substrate of a semiconductor-on-insulator (SOI) layer. A dielectric liner stack of a dielectric metal oxide layer and a silicon nitride layer is formed in the shallow trench, followed by deposition of a shallow trench isolation fill portion. The dielectric liner stack is removed from above a top surface of a top semiconductor portion, followed by removal of a silicon nitride pad layer and an upper vertical portion of the dielectric metal oxide layer. A divot laterally surrounding a stack of a top semiconductor portion and a buried insulator portion is filled with a silicon nitride portion. Gate structures and source/drain structures are subsequently formed. The silicon nitride portion or the dielectric metal oxide layer functions as a stopping layer during formation of source/drain contact via holes, thereby preventing electrical shorts between source/drain contact via structures and the handle substrate.

摘要翻译： 形成浅沟槽以延伸到绝缘体上半导体（SOI）层的处理衬底中。 在浅沟槽中形成介质金属氧化物层和氮化硅层的电介质衬垫层，随后沉积浅沟槽隔离填充部分。 介电衬垫堆叠从顶部半导体部分的顶表面上方移除，随后除去介电金属氧化物层的氮化硅衬垫层和上部垂直部分。 横向围绕顶部半导体部分和掩埋绝缘体部分的堆叠的边角填充有氮化硅部分。 随后形成栅极结构和源极/漏极结构。 氮化硅部分或电介质金属氧化物层在形成源极/漏极接触通孔期间用作停止层，从而防止源极/漏极接触通孔结构和处理衬底之间的电短路。

公开(公告)号：US20140070357A1

公开(公告)日：2014-03-13

申请号：US13611182

申请日：2012-09-12

申请人： Kangguo Cheng ,  Balasubramanian S. Haran ,  Shom Ponoth

发明人： Kangguo Cheng ,  Balasubramanian S. Haran ,  Shom Ponoth

IPC分类号： H01L29/06 ,  H01L21/762

CPC分类号： H01L27/1203 ,  H01L21/31144 ,  H01L21/76283 ,  H01L21/84 ,  H01L29/06 ,  H01L29/66772 ,  H01L29/78654

摘要： A semiconductor substrate having an isolation region and method of forming the same. The method includes the steps of providing a substrate having a substrate layer, a buried oxide (BOX), a silicon on insulator (SOI) layer, a pad oxide layer, and a pad nitride layer, forming a shallow trench region, etching the pad oxide layer to form ears and etching the BOX layer to form undercuts, depositing a liner on the shallow trench region, depositing a soft mask over the surface of the shallow trench region, filling the shallow trench region, etching the soft mask so that it is recessed to the top of the BOX layer, etching the liner off certain regions, removing the soft mask, and filling and polishing the shallow trench region. The liner prevents shorting of the semiconductor device when the contacts are misaligned.

摘要翻译： 具有隔离区域的半导体基板及其形成方法。 该方法包括以下步骤：提供具有衬底层，掩埋氧化物（BOX），绝缘体上硅（SOI）层，衬垫氧化物层和衬垫氮化物层的衬底，形成浅沟槽区，蚀刻衬垫 氧化层以形成耳朵并蚀刻BOX层以形成底切，在浅沟槽区域上沉积衬垫，在浅沟槽区域的表面上沉积软掩模，填充浅沟槽区域，蚀刻软掩模，使得它 凹陷到BOX层的顶部，在某些区域蚀刻衬垫，去除软掩模，以及填充和抛光浅沟槽区域。 当触点不对准时，衬垫防止半导体器件的短路。

公开(公告)号：US20140061930A1

公开(公告)日：2014-03-06

申请号：US13604660

申请日：2012-09-06

申请人： Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

发明人： Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L23/528 ,  H01L21/31144 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76831 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/0001 ,  H01L2924/00

摘要： A method is provided that includes first etching a substrate according to a first mask. The first etching forms a first etch feature in the substrate to a first depth. The first etching also forms a sliver opening in the substrate. The sliver opening may then be filled with a fill material. A second mask may be formed by removing a portion of the first mask. The substrate exposed by the second mask may be etched with a second etch, in which the second etching is selective to the fill material. The second etching extends the first etch feature to a second depth that is greater than the first depth, and the second etch forms a second etch feature. The first etch feature and the second etch feature may then be filled with a conductive metal.

摘要翻译： 提供了一种方法，其包括首先根据第一掩模蚀刻衬底。 第一蚀刻在衬底中形成第一深度的第一蚀刻特征。 第一蚀刻还在衬底中形成条条开口。 然后可以用填充材料填充条子开口。 可以通过去除第一掩模的一部分来形成第二掩模。 可以用第二蚀刻蚀刻由第二掩模曝光的衬底，其中第二蚀刻对填充材料是选择性的。 第二蚀刻将第一蚀刻特征延伸到大于第一深度的第二深度，并且第二蚀刻形成第二蚀刻特征。 然后可以用导电金属填充第一蚀刻特征和第二蚀刻特征。