公开(公告)号：US20240045621A1

公开(公告)日：2024-02-08

申请号：US18382767

申请日：2023-10-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Xiaojia SONG ,  Stephen Garry FISCHER

IPC: G06F3/06 ,  G06F13/16

CPC classification number: G06F3/067 ,  G06F3/0611 ,  G06F3/0604 ,  G06F13/16 ,  G06F3/0679 ,  G06F2213/0026 ,  G06F2212/1024

Abstract: A server system includes a first plurality of mass-storage devices, a central processing unit (CPU), and at least one near data processing (NDP) engine. The CPU is coupled to the first plurality of the mass-storage devices, such as solid-state drive (SSD) devices, and the at least one NDP engine is associated with a second plurality of the mass-storage devices and interposed between the CPU and the second plurality of the mass-storage devices associated with the NDP engine. The second plurality of the mass-storage devices is less than or equal to the first plurality of the mass-storage devices. A number of NDP engines may be based on a minimum bandwidth of a bandwidth associated with the CPU, a bandwidth associated with a network, a bandwidth associated with the communication fabric and a bandwidth associated with all NDP engines divided by a bandwidth associated with a single NDP engine.

公开(公告)号：US11886742B2

公开(公告)日：2024-01-30

申请号：US17500170

申请日：2021-10-13

Applicant: KIOXIA CORPORATION

Inventor： Takashi Yamaguchi

IPC: G06F3/06 ,  G06F13/16 ,  G06F13/42

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679 ,  G06F13/1668 ,  G06F13/4282 ,  G06F2213/0026

Abstract: According to one embodiment, a memory system is capable of being connected to a host. The memory system includes a nonvolatile memory and a controller that receives information regarding an operating state of the host. The controller controls the nonvolatile memory according to commands from the host and selects a parameter for interrupt coalescing for transmissions to the host of interrupts related to command completion notices for the commands from the host based on the information regarding the operating state of the host.

公开(公告)号：US20240020256A1

公开(公告)日：2024-01-18

申请号：US18375054

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Kevan A. Lillie ,  Shlomi Lalush ,  Yaakov Dalsace ,  Adee Ofir Ran ,  Assaf Benhamou ,  David Golodni ,  Itay Tamir ,  Amir Laufer

IPC: G06F13/38 ,  G06F13/16 ,  G06F13/20 ,  G06F9/4401 ,  G06F30/18

CPC classification number: G06F13/382 ,  G06F13/16 ,  G06F13/20 ,  G06F9/4411 ,  G06F30/18 ,  G06F2213/0026 ,  G06F2213/0024

Abstract: Techniques and apparatus to provide for interactions between system components are described. In one embodiment, an apparatus to provide a component interface, the apparatus comprising at least one memory, a first component comprising at least one register, logic, at least a portion of comprised in hardware, the logic to define at least one interface field stored in the at least one register, generate an interface with a second component based on the at least one interface field, and receive interface information from the second component via the interface, the interface information comprising at least one value for the at least one interface field.

公开(公告)号：US20240020247A1

公开(公告)日：2024-01-18

申请号：US18373711

申请日：2023-09-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Oscar P. Pinto ,  Robert Brennan

IPC: G06F13/16

CPC classification number: G06F13/1668 ,  G06F2213/0026

Abstract: Embodiments of the present invention include a drive-to-drive storage system comprising a host server having a host CPU and a host storage drive, one or more remote storage drives, and a peer-to-peer link connecting the host storage drive to the one or more remote storage drives. The host storage drive includes a processor and a memory, wherein the memory has stored thereon instructions that, when executed by the processor, causes the processor to transfer data from the host storage drive via the peer-to-peer link to the one or more remote storage drives when the host CPU issues a write command.

公开(公告)号：US11877416B2

公开(公告)日：2024-01-16

申请号：US17583328

申请日：2022-01-25

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Yu Lih Chuang ,  Yen-Tang Chang ,  Heather Louise Burnam Volesky ,  Jonathan D. Bassett ,  Wen Bin Lin ,  Chao-Wen Cheng

IPC: H05K7/14 ,  G06F13/42 ,  H05K1/14 ,  H05K3/36

CPC classification number: H05K7/1444 ,  G06F13/4226 ,  H05K7/1418 ,  G06F2213/0024 ,  G06F2213/0026 ,  H05K1/141

Abstract: In example implementations, an apparatus is provided. The apparatus includes a riser card body, a first interface, a first 2×8 slot on a surface of the riser card body, and a second 2×8 slot on a same side of the surface of the riser card body as the first 2×8 slot. The first interface includes a first set of fingers and a second set of fingers at an end of the riser card body to connect to a peripheral component interconnect express (PCIe) slot of a motherboard. The first 2×8 slot and the second 2×8 slot are positioned perpendicular to the PCIe slot of the motherboard.

公开(公告)号：US11876702B2

公开(公告)日：2024-01-16

申请号：US17594815

申请日：2020-03-23

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Abdulla M. Bataineh ,  Thomas L. Court ,  Hess M. Hodge

IPC: G06F13/14 ,  H04L45/02 ,  H04L45/028 ,  H04L45/125 ,  H04L45/00 ,  H04L45/122 ,  H04L47/76 ,  H04L49/15 ,  H04L49/00 ,  H04L69/40 ,  H04L47/10 ,  H04L49/9005 ,  H04L47/34 ,  H04L67/1097 ,  G06F13/16 ,  H04L45/021 ,  H04L47/12 ,  G06F13/42 ,  H04L47/2441 ,  H04L47/30 ,  H04L47/62 ,  H04L47/24 ,  H04L49/90 ,  G06F13/38 ,  G06F13/40 ,  H04L45/745 ,  H04L47/2483 ,  H04L47/629 ,  H04L47/80 ,  H04L49/101 ,  H04L45/12 ,  H04L47/122 ,  G06F12/1036 ,  G06F15/173 ,  H04L43/10 ,  H04L45/42 ,  H04L47/11 ,  G06F12/0862 ,  G06F12/1045 ,  H04L47/32 ,  G06F9/54 ,  G06F9/50 ,  H04L47/22 ,  H04L47/52 ,  H04L47/6275 ,  H04L45/24 ,  H04L45/7453 ,  H04L45/16 ,  H04L69/22 ,  H04L47/762 ,  H04L47/78 ,  H04L47/20 ,  H04L49/9047 ,  H04L1/00 ,  H04L43/0876 ,  H04L47/2466 ,  H04L47/625 ,  H04L69/28

CPC classification number: H04L45/02 ,  G06F9/505 ,  G06F9/546 ,  G06F12/0862 ,  G06F12/1036 ,  G06F12/1063 ,  G06F13/14 ,  G06F13/16 ,  G06F13/1642 ,  G06F13/1673 ,  G06F13/1689 ,  G06F13/385 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4221 ,  G06F15/17331 ,  H04L1/0083 ,  H04L43/0876 ,  H04L43/10 ,  H04L45/021 ,  H04L45/028 ,  H04L45/122 ,  H04L45/123 ,  H04L45/125 ,  H04L45/16 ,  H04L45/20 ,  H04L45/22 ,  H04L45/24 ,  H04L45/38 ,  H04L45/42 ,  H04L45/46 ,  H04L45/566 ,  H04L45/70 ,  H04L45/745 ,  H04L45/7453 ,  H04L47/11 ,  H04L47/12 ,  H04L47/122 ,  H04L47/18 ,  H04L47/20 ,  H04L47/22 ,  H04L47/24 ,  H04L47/2441 ,  H04L47/2466 ,  H04L47/2483 ,  H04L47/30 ,  H04L47/32 ,  H04L47/323 ,  H04L47/34 ,  H04L47/39 ,  H04L47/52 ,  H04L47/621 ,  H04L47/626 ,  H04L47/629 ,  H04L47/6235 ,  H04L47/6275 ,  H04L47/76 ,  H04L47/762 ,  H04L47/781 ,  H04L47/80 ,  H04L49/101 ,  H04L49/15 ,  H04L49/30 ,  H04L49/3009 ,  H04L49/3018 ,  H04L49/3027 ,  H04L49/90 ,  H04L49/9005 ,  H04L49/9021 ,  H04L49/9036 ,  H04L49/9047 ,  H04L67/1097 ,  H04L69/22 ,  H04L69/40 ,  G06F2212/50 ,  G06F2213/0026 ,  G06F2213/3808 ,  H04L69/28

Abstract: A network interface controller (NIC) capable of facilitating efficient memory address translation is provided. The NIC can be equipped with a host interface, a cache, and an address translation unit (ATU). During operation, the ATU can determine an operating mode. The operating mode can indicate whether the ATU is to perform a memory address translation at the NIC. The ATU can then determine whether a memory address indicated in the memory access request is available in the cache. If the memory address is not available in the cache, the ATU can perform an operation on the memory address based on the operating mode.

公开(公告)号：US11875172B2

公开(公告)日：2024-01-16

申请号：US17107568

申请日：2020-11-30

Applicant: VMware LLC

Inventor： Renaud B. Voltz

IPC: G06F9/455 ,  G06F9/54 ,  G06F13/42 ,  G06F9/4401 ,  G06F9/50

CPC classification number: G06F9/45558 ,  G06F9/4406 ,  G06F9/45541 ,  G06F9/547 ,  G06F13/4221 ,  G06F9/5077 ,  G06F2009/4557 ,  G06F2009/45579 ,  G06F2009/45591 ,  G06F2009/45595 ,  G06F2213/0026

Abstract: Some embodiments provide a method for operating a physical server in a network. The method stores multiple copies of a virtual machine (VM) image at a network-accessible storage. The method uses a first copy of the VM image as a virtual disk to execute a VM on a hypervisor of a first physical computing device. The method uses a second copy of the VM image as a virtual disk accessible via a smart network interface controller (NIC) of a second physical computing device to execute an operating system of the second physical computing device.

公开(公告)号：US11874785B1

公开(公告)日：2024-01-16

申请号：US17949151

申请日：2022-09-20

Applicant: Amazon Technologies, Inc.

Inventor： Patricio Kaplan ,  Ron Diamant

IPC: G06F3/06 ,  G06F13/28

CPC classification number: G06F13/28 ,  G06F3/0604 ,  G06F3/0655 ,  G06F3/0673 ,  G06F2213/0026 ,  G06F2213/28

Abstract: In one example, an apparatus comprises: a local on-chip memory; a computation engine configured to generate local data and to store the local data at the local on-chip memory; and a controller. The apparatus is configured to be coupled with a second device via an interconnect, the second device comprising a local memory. The controller is configured to: fetch the local data from the local on-chip memory; fetch remote data generated by another device from a local off-chip memory; generate output data based on combining the local data and the remote data; and store, via the interconnect, the output data at the local memory of the second device.

公开(公告)号：US11874689B2

公开(公告)日：2024-01-16

申请号：US17749133

申请日：2022-05-19

Applicant: SK hynix Inc.

Inventor： Yong Tae Jeon ,  Ji Woon Yang ,  Dae Sik Park

IPC: G06F13/28 ,  G06F13/42

CPC classification number: G06F13/28 ,  G06F13/4221 ,  G06F2213/0026

Abstract: A Peripheral Component Interconnect Express (PCIe) interface device may include a PCIe layer, a link training module, a PCIe register, and a PCIe controller. The PCIe layer may perform communication between a host and a Direct Memory Access (DMA) device. The link training module may perform a link training for the host. The PCIe register may store data information on the PCIe layer. The PCIe controller may switch an operating clock from a PCIe clock, generated based on a reference clock, to an internal clock, process data of the PCIe layer on the basis of the internal clock, and control the link training module to recover a link for the host, when a reset signal received from the host is asserted or the reference clock is off.

公开(公告)号：US11868209B2

公开(公告)日：2024-01-09

申请号：US18046453

申请日：2022-10-13

Applicant: Ampere Computing LLC

Inventor： Matthew Robert Erler ,  Robert James Safranek ,  Robert Joseph Toepfer ,  Sandeep Brahmadathan ,  Shailendra Ramrao Chavan ,  Jonglih Yu

IPC: G06F11/00 ,  G06F11/10 ,  G06F13/42

CPC classification number: G06F11/1004 ,  G06F13/4221 ,  G06F13/4282 ,  G06F2213/0024 ,  G06F2213/0026

Abstract: The system or device may build one or more data packets by dividing a given payload for a packet into data blocks and inserting data checks for each data block sequentially into the packet payload. The device may generate, for each of the data blocks, a corresponding data check block corresponding to data in each data block. The device may send or arrange the data blocks and the corresponding data check blocks such that each of the data blocks is followed by the corresponding error check block in the packet. Using the corresponding check block, each of the data blocks is independently verifiable, so that the data blocks may be used upon receipt, even if the payload is not completely received.