公开(公告)号：US12213392B2

公开(公告)日：2025-01-28

申请号：US17362670

申请日：2021-06-29

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Philippe Boivin

IPC: H10N70/00 ,  H10B63/00 ,  H10N70/20

Abstract: Memory devices and methods of manufacturing such devices are provided herein. In at least one embodiment, a memory device includes a plurality of phase-change memory cells. An electrically-insulating layer covers lateral walls of each of the phase-change memory cells, and a thermally-insulating material is disposed on the electrically-insulating layer and covers the lateral walls of the phase-change memory cells.

公开(公告)号：US20250023569A1

公开(公告)日：2025-01-16

申请号：US18899458

申请日：2024-09-27

Applicant: STMICROELECTRONICS INTERNATIONAL N.V. ,  STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Marco Bildgen

IPC: H03K19/17768 ,  H03K19/08 ,  H03K19/1776

Abstract: In an embodiment an integrated device includes a first physical unclonable function module configured to generate an initial data group and management module configured to generate an output data group from at least the initial data group, authorize only D successive deliveries of the output data group on a first output interface of the device, D being a non-zero positive integer, and prevent any new generation of the output data group.

公开(公告)号：US12113444B2

公开(公告)日：2024-10-08

申请号：US17856657

申请日：2022-07-01

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics S.r.l.

Inventor： Vanni Poletto ,  Antoine Pavlin

IPC: H02M3/158 ,  B60L53/22 ,  B60L58/20

CPC classification number: H02M3/1586 ,  B60L53/22 ,  B60L58/20 ,  B60L2210/12 ,  B60L2210/14

Abstract: In an embodiment, a phase circuit includes: a bidirectional output stage configured to be coupled between a first battery and a second battery; a memory configured to store a number of active phases, and an identifier; and a synchronization circuit configured to receive a first clock signal and determine a start time of a switching cycle of the bidirectional output stage based on the number of active phases, the identifier, and the first clock signal, where the phase circuit is configured to control the timing of the switching of the bidirectional output stage based on the start time.

公开(公告)号：US20240312977A1

公开(公告)日：2024-09-19

申请号：US18668639

申请日：2024-05-20

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal FORNARA ,  Roberto SIMOLA

IPC: H01L27/01 ,  H01L21/70 ,  H10B41/41 ,  H10B41/42

CPC classification number: H01L27/016 ,  H01L21/707 ,  H10B41/41 ,  H10B41/42

Abstract: An integrated circuit includes a semiconductor substrate, a conductive layer above a front face of the substrate, a first metal track in a first metal level, and a pre-metal dielectric region located between the conductive layer and the first metal level. A metal-insulator-metal-type capacitive structure is located in a trench within the pre-metal dielectric region. The capacitive structure includes a first metal layer electrically connected with the conductive layer, a second metal layer electrically connected with the first metal track, and a dielectric layer between the first metal layer and the second metal layer.

公开(公告)号：US20240304237A1

公开(公告)日：2024-09-12

申请号：US18583574

申请日：2024-02-21

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Christophe GONCALVES ,  Marc BATTISTA ,  Francois TAILLIET

IPC: G11C11/4091 ,  G11C11/4096 ,  G11C11/4099

CPC classification number: G11C11/4091 ,  G11C11/4096 ,  G11C11/4099

Abstract: The present disclosure relates to a memory device including a sense amplifier, wherein the amplifier comprises a first inverter, wherein an input and an output of the inverter are coupled to a first transistor configured to be switched on during a step of pre-charging of a memory cell.

公开(公告)号：US12086008B2

公开(公告)日：2024-09-10

申请号：US17942354

申请日：2022-09-12

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics Design and Application S.R.O.

Inventor： Jerome Lacan ,  Remi Collette ,  Christophe Eva ,  Milan Komarek

IPC: G06F1/3225 ,  G06F1/3287 ,  H03K19/017

CPC classification number: G06F1/3225 ,  G06F1/3287 ,  H03K19/01742

Abstract: A system includes a control unit configured to be electrically connected to an input of a memory via a communication interface. The control unit includes a first power supply sector configured to be powered when the control unit is in an operating mode and a second power supply sector configured to be powered when the control unit is in the operating mode and in a low consumption mode. In the first power supply sector, the control unit includes a first configuration circuit operating to configure a polarization value of the input of the memory via the communication interface for the operating mode. In the second power supply sector, the control unit includes a second configuration circuit operating to configure a polarization value of the input of the memory via the communication interface for the low consumption mode.

公开(公告)号：US12063775B2

公开(公告)日：2024-08-13

申请号：US18484906

申请日：2023-10-11

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Abderrezak Marzaki ,  Mathieu Lisart ,  Benoit Froment

IPC: H10B20/00 ,  H01L23/00 ,  G11C16/04

CPC classification number: H10B20/367 ,  G11C16/0466 ,  H01L23/57

Abstract: The present description concerns a ROM including at least one first rewritable memory cell. In an embodiment, a method of manufacturing a read-only memory (ROM) comprising a plurality of memory cells is proposed. Each of the plurality of memory cells includes a rewritable first transistor and a rewritable second transistor. An insulated gate of the rewritable first transistor is connected to an insulated gate of the rewritable second transistor. The method includes successively depositing, on a semiconductor structure, a first insulating layer and a first gate layer, wherein the first insulating layer is arranged between the semiconductor structure and the first gate layer, wherein the rewritable second transistor further includes a well-formed between an associated first insulating layer and the semiconductor structure, and wherein the rewritable first insulating layer is in direct contact with the semiconductor structure; and successively depositing a second insulating layer and a second gate layer.

公开(公告)号：US20240267050A1

公开(公告)日：2024-08-08

申请号：US18641199

申请日：2024-04-19

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Jean-Francois LINK ,  Mark WALLIS ,  Joran PANTEL

IPC: H03K19/17736 ,  H03K19/173

CPC classification number: H03K19/17744 ,  H03K19/1737 ,  H03K19/1774

Abstract: A system on chip includes a programmable logic array. The system on chip also includes a signal conditioner coupled to a data input of the programmable logic array and configured to condition a data signal prior to processing the data signal with the programmable logic array. The signal conditioner can selectively condition the signal by one or both of synchronizing the data signal with a clock signal of the programmable logic array and generating a pulse from the data signal with an edge detector.

公开(公告)号：US12052861B2

公开(公告)日：2024-07-30

申请号：US18321487

申请日：2023-05-22

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet

IPC: H01L21/00 ,  G11C7/18 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H10B41/00 ,  H10B41/35 ,  H01L29/788

CPC classification number: H10B41/00 ,  G11C7/18 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/24 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66825 ,  H10B41/35 ,  H01L29/7881

Abstract: An EEPROM memory integrated circuit includes memory cells arranged in a memory plane. Each memory cell includes an access transistor in series with a state transistor. Each access transistor is coupled, via its source region, to the corresponding source line and each state transistor is coupled, via its drain region, to the corresponding bit line. The floating gate of each state transistor rests on a dielectric layer having a first part with a first thickness, and a second part with a second thickness that is less than the first thickness. The second part is located on the source side of the state transistor.

公开(公告)号：US12035522B2

公开(公告)日：2024-07-09

申请号：US17700323

申请日：2022-03-21

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Franck Melul ,  Abderrezak Marzaki ,  Madjid Akbal

IPC: H10B41/35 ,  G11C16/16 ,  G11C16/26 ,  G11C16/34 ,  H01L21/28 ,  H01L29/66 ,  H01L29/788 ,  H10B41/10

CPC classification number: H10B41/35 ,  G11C16/16 ,  G11C16/26 ,  G11C16/34 ,  H01L29/66825 ,  H01L29/7884 ,  H01L29/40114 ,  H01L29/7883 ,  H10B41/10

Abstract: In an embodiment a memory cell includes a first doped well of a first conductivity type in contact with a second doped well of a second conductivity type, the second conductivity type being opposite to the first conductivity type, a third doped well of the second conductivity type in contact with a fourth doped well of the first conductivity type, a first wall in contact with the second and fourth wells, the first wall including a conductive or semiconductor core and an insulating sheath, a stack of layers including a first insulating layer, a first semiconductor layer, a second insulating layer and a second semiconductor layer at least partially covering the second and fourth wells and a third semiconductor layer located below the second and fourth wells and the first wall.