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    Method to increase the compressive stress of PECVD silicon nitride films
    63.
    发明授权
    Method to increase the compressive stress of PECVD silicon nitride films 有权
    增加PECVD氮化硅膜的压应力的方法

    公开(公告)号：US07732342B2

    公开(公告)日：2010-06-08

    申请号：US11398146

    申请日：2006-04-05

    Applicant: Mihaela Balseanu ,  Li-Qun Xia ,  Vladimir Zubkov ,  Mei-Yee Shek ,  Isabelita Rolfox ,  Hichem M'Saad

    Inventor： Mihaela Balseanu ,  Li-Qun Xia ,  Vladimir Zubkov ,  Mei-Yee Shek ,  Isabelita Rolfox ,  Hichem M'Saad

    IPC: H01L21/302

    CPC classification number: C23C16/345 ,  C23C16/0245 ,  C23C16/0272 ,  C23C16/56 ,  H01L21/3185

    Abstract: Compressive stress in a film of a semiconductor device may be controlled utilizing one or more techniques, employed alone or in combination. A first set of embodiments increase silicon nitride compressive stress by adding hydrogen to the deposition chemistry, and reduce defects in a device fabricated with a high compressive stress silicon nitride film formed in the presence of hydrogen gas. A silicon nitride film may comprise an initiation layer formed in the absence of a hydrogen gas flow, underlying a high stress nitride layer formed in the presence of a hydrogen gas flow. A silicon nitride film formed in accordance with an embodiment of the present invention may exhibit a compressive stress of 2.8 GPa or higher.

    Abstract translation: 半导体器件的膜中的压缩应力可以利用单独使用或组合使用的一种或多种技术来控制。 第一组实施例通过向沉积化学品加入氢而增加氮化硅压缩应力，并且减少在氢气存在下形成的高压缩应力氮化硅膜制造的器件中的缺陷。 氮化硅膜可以包括在不存在氢气流的情况下形成的起始层，位于在氢气流的存在下形成的高应力氮化物层的下面。 根据本发明的实施方案形成的氮化硅膜可以表现出2.8GPa或更高的压缩应力。

    Selective copper-silicon-nitride layer formation for an improved dielectric film/copper line interface
    64.
    发明授权
    Selective copper-silicon-nitride layer formation for an improved dielectric film/copper line interface 有权
    用于改进的介电膜/铜线接口的选择性铜 - 氮化硅层形成

    公开(公告)号：US07718548B2

    公开(公告)日：2010-05-18

    申请号：US11950691

    申请日：2007-12-05

    Applicant: Sang M. Lee ,  Vladimir Zubkov ,  Zhenijiang Cui ,  Meiyee Shek ,  Li-Qun Xia ,  Hichem M'Saad

    Inventor： Sang M. Lee ,  Vladimir Zubkov ,  Zhenijiang Cui ,  Meiyee Shek ,  Li-Qun Xia ,  Hichem M'Saad

    IPC: H01L21/469

    CPC classification number: H01L21/76856 ,  H01L21/76826 ,  H01L21/76849 ,  H01L21/76864 ,  H01L21/76867

    Abstract: A process to form a copper-silicon-nitride layer on a copper surface on a semiconductor wafer is described. The process may include the step of exposing the wafer to a first plasma made from helium. The process may also include exposing the wafer to a second plasma made from a reducing gas, where the second plasma removes copper oxide from the copper surface, and exposing the wafer to silane, where the silane reacts with the copper surface to selectively form copper silicide. The process may further include exposing the wafer to a third plasma made from ammonia and molecular nitrogen to form the copper silicon nitride layer.

    Abstract translation: 描述了在半导体晶片上的铜表面上形成铜 - 氮化硅层的工艺。 该方法可以包括将晶片暴露于由氦制成的第一等离子体的步骤。 该方法还可以包括将晶片暴露于由还原气体制成的第二等离子体，其中第二等离子体从铜表面去除氧化铜，并将晶片暴露于硅烷，硅烷与铜表面反应以选择性地形成硅化铜 。 该方法还可以包括将晶片暴露于由氨和分子氮制成的第三等离子体，以形成铜氮化硅层。

    Memory cell having stressed layers
    65.
    发明授权
    Memory cell having stressed layers 失效
    具有应力层的记忆单元

    公开(公告)号：US07678662B2

    公开(公告)日：2010-03-16

    申请号：US11609851

    申请日：2006-12-12

    Applicant: Reza Arghavani ,  Ellie Yieh ,  Hichem M'Saad

    Inventor： Reza Arghavani ,  Ellie Yieh ,  Hichem M'Saad

    IPC: H01L21/76

    CPC classification number: H01L29/7846 ,  H01L27/105 ,  H01L27/1052 ,  H01L29/66825 ,  H01L29/7883

    Abstract: A memory cell comprises a p-doped substrate with a pair of spaced apart n-doped regions on the substrate that form a source and drain about the channel. A stack of layers on the channel comprises, in sequence, (i) a tunnel oxide layer, (ii) a floating gate, (iii) an inter-gate dielectric, and (iv) a control gate. A polysilicon layer is on the source and drain. A cover layer covering the stack of layers comprises a spacer layer and a pre-metal-deposition layer. Optionally, contacts are used to contact each of the source, drain, and silicide layers, and each have exposed portions. A shallow isolation trench is provided about n-doped regions, the trench comprising a stressed silicon oxide layer having a tensile stress of at least about 200 MPa. The stressed layer reduces leakage of charge held in the floating gate during operation of the memory cell.

    Abstract translation: 存储单元包括在基板上具有一对间隔开的n掺杂区域的p掺杂衬底，其在沟道周围形成源极和漏极。 通道上的层叠层包括（i）隧道氧化物层，（ii）浮动栅极，（iii）栅极间电介质和（iv）控制栅极。 源极和漏极上的多晶硅层。 覆盖层叠层的覆盖层包括间隔层和预金属沉积层。 可选地，使用触点来接触源极，漏极和硅化物层中的每一个，并且每个都具有暴露部分。 围绕n掺杂区域提供浅的隔离沟槽，沟槽包括具有至少约200MPa的拉伸应力的应力氧化硅层。 应力层在存储器单元的操作期间减少了保持在浮动栅极中的电荷的泄漏。

    SELECTIVE COPPER-SILICON-NITRIDE LAYER FORMATION FOR AN IMPROVED DIELECTRIC FILM/COPPER LINE INTERFACE
    69.
    发明申请
    SELECTIVE COPPER-SILICON-NITRIDE LAYER FORMATION FOR AN IMPROVED DIELECTRIC FILM/COPPER LINE INTERFACE 有权
    改进的电介质膜/铜线接口的选择性铜 - 氮 - 氮层形成

    公开(公告)号：US20080213997A1

    公开(公告)日：2008-09-04

    申请号：US11950691

    申请日：2007-12-05

    Applicant: Sang M. Lee ,  Vladimir Zubkov ,  Zhenijiang Cui ,  Meiyee Shek ,  Li-Qun Xia ,  Hichem M'Saad

    Inventor： Sang M. Lee ,  Vladimir Zubkov ,  Zhenijiang Cui ,  Meiyee Shek ,  Li-Qun Xia ,  Hichem M'Saad

    IPC: H01L21/768

    CPC classification number: H01L21/76856 ,  H01L21/76826 ,  H01L21/76849 ,  H01L21/76864 ,  H01L21/76867

    Abstract: A process to form a copper-silicon-nitride layer on a copper surface on a semiconductor wafer is described. The process may include the step of exposing the wafer to a first plasma made from helium. The process may also include exposing the wafer to a second plasma made from a reducing gas, where the second plasma removes copper oxide from the copper surface, and exposing the wafer to silane, where the silane reacts with the copper surface to selectively form copper silicide. The process may further include exposing the wafer to a third plasma made from ammonia and molecular nitrogen to form the copper silicon nitride layer.

    Abstract translation: 描述了在半导体晶片上的铜表面上形成铜 - 氮化硅层的工艺。 该方法可以包括将晶片暴露于由氦制成的第一等离子体的步骤。 该方法还可以包括将晶片暴露于由还原气体制成的第二等离子体，其中第二等离子体从铜表面去除氧化铜，并将晶片暴露于硅烷，硅烷与铜表面反应以选择性地形成硅化铜 。 该方法还可以包括将晶片暴露于由氨和分子氮制成的第三等离子体，以形成铜氮化硅层。

    NOVEL AIR GAP INTEGRATION SCHEME
    70.
    发明申请
    NOVEL AIR GAP INTEGRATION SCHEME 失效
    新的空气隙整合方案

    公开(公告)号：US20080182404A1

    公开(公告)日：2008-07-31

    申请号：US12017930

    申请日：2008-01-22

    Applicant: ALEXANDROS T. DEMOS ,  Li-Qun Xia ,  Bok Hoen Kim ,  Derek R. Witty ,  Hichem M'Saad

    Inventor： ALEXANDROS T. DEMOS ,  Li-Qun Xia ,  Bok Hoen Kim ,  Derek R. Witty ,  Hichem M'Saad

    IPC: H01L21/4763

    CPC classification number: H01L21/7682 ,  C23C16/401 ,  C23C16/56 ,  H01L21/02115 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02351 ,  H01L21/02362 ,  H01L21/3146 ,  H01L21/31633 ,  H01L21/31695 ,  H01L21/76811 ,  H01L21/76835 ,  H01L2221/1047 ,  Y10S438/931

    Abstract: Methods are provided for forming a structure that includes an air gap. In one embodiment, a method is provided for forming a damascene structure comprises depositing a porous low dielectric constant layer by a method including reacting an organosilicon compound and a porogen-providing precursor, depositing a porogen-containing material, and removing at least a portion of the porogen-containing material, depositing an organic layer on the porous low dielectric constant layer by reacting the porogen-providing precursor, forming a feature definition in the organic layer and the porous low dielectric constant layer, filing the feature definition with a conductive material therein, depositing a mask layer on the organic layer and the conductive material disposed in the feature definition, forming apertures in the mask layer to expose the organic layer, removing a portion or all of the organic layer through the apertures, and forming an air gap adjacent the conductive material.

    Abstract translation: 提供了用于形成包括气隙的结构的方法。 在一个实施例中，提供了一种用于形成镶嵌结构的方法，包括通过包括使有机硅化合物和致孔剂提供前体反应的方法沉积多孔低介电常数层，沉积含致孔剂的材料，以及除去至少一部分 含致孔剂的材料，通过使造孔剂提供前体反应，在有机层中形成特征定义和多孔低介电常数层，在多孔低介电常数层上沉积有机层，用导电材料填充特征定义 在有机层上沉积掩模层和设置在特征定义中的导电材料，在掩模层中形成孔以暴露有机层，通过孔去除部分或全部有机层，并形成相邻的气隙 导电材料。

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