公开(公告)号：US08508187B2

公开(公告)日：2013-08-13

申请号：US13028219

申请日：2011-02-16

Applicant: Wen-Shu Chiang ,  Chin-Pin Chien ,  An-Hung Lin

Inventor： Wen-Shu Chiang ,  Chin-Pin Chien ,  An-Hung Lin

IPC: H02J7/00 ,  B60K6/20

CPC classification number: H02J7/0004 ,  B60L11/1816 ,  B60L11/1824 ,  B60L11/1844 ,  B60L11/1846 ,  B60L2230/40 ,  B60L2240/70 ,  Y02E60/721 ,  Y02T10/7005 ,  Y02T10/7088 ,  Y02T10/7291 ,  Y02T90/121 ,  Y02T90/128 ,  Y02T90/14 ,  Y02T90/16 ,  Y02T90/163 ,  Y02T90/168 ,  Y02T90/169 ,  Y04S10/126 ,  Y04S30/12 ,  Y04S30/14

Abstract: An interactive charging management system and a method thereof are provided. The method is applicable to a plurality of electric vehicles, and which includes dynamically adjusting usable power information respectively provided by a plurality of charging posts respectively corresponding to and coupled to the electric vehicles according to demand power information of the respective electric vehicles; and making the charging posts non-uniformly provide a plurality of charging powers to the respective electric vehicles according to the adjusted usable power information.

Abstract translation: 提供了交互式计费管理系统及其方法。 该方法适用于多个电动车辆，其包括根据各电动车辆的需求功率信息动态调整分别对应于电动车辆并耦合到电动车辆的多个充电站分别提供的可用功率信息; 并且根据调整后的可用功率信息使充电柱不均匀地向各电动车辆提供多个充电功率。

公开(公告)号：US20130201594A1

公开(公告)日：2013-08-08

申请号：US13365556

申请日：2012-02-03

Applicant: Pao-Hung LIN ,  Hung-Lung Wang

Inventor： Pao-Hung LIN ,  Hung-Lung Wang

IPC: H01H47/22

CPC classification number: H01H47/22 ,  H01H47/12

Abstract: The present invention relates to a driving circuit for relay, which uses N relays with their coils coupled to each other. One of the relays is coupled to a driving power supply. A switching control circuit is coupled to a second relay and a reference voltage for controlling on/off of the plurality of relays. A driving control circuit is coupled to the plurality of relays for controlling excitation of the plurality of relays. After the coils of the relays are excited by the driving control circuit, the voltage of a single coil is dropped to one Nth of the driving voltage. Thereby, the power consumption of the coils of the relays can be reduced, and hence enhancing the lifetime and reliability of the relays.

Abstract translation: 本发明涉及一种用于继电器的驱动电路，其使用N个继电器，它们的线圈彼此耦合。 其中一个继电器耦合到驱动电源。 开关控制电路耦合到第二继电器和用于控制多个继电器的开/关的参考电压。 驱动控制电路耦合到多个继电器，用于控制多个继电器的激励。 在继电器的线圈被驱动控制电路激励之后，单个线圈的电压下降到驱动电压的十分之一。 因此，可以减少继电器的线圈的功耗，从而提高继电器的寿命和可靠性。

公开(公告)号：US08491176B2

公开(公告)日：2013-07-23

申请号：US12963639

申请日：2010-12-09

Applicant: Sheng-Hung Lin ,  Jung-Min Hwang ,  Udo Custodis ,  Shih-Yuan Yu

Inventor： Sheng-Hung Lin ,  Jung-Min Hwang ,  Udo Custodis ,  Shih-Yuan Yu

IPC: G02B6/10

CPC classification number: G02B6/0036 ,  G02B6/0068

Abstract: A light guide plate (LGP) includes a first surface, a second surface, and a plurality of light incident surfaces. The first surface is a light-emitting surface. The light incident surfaces connect the first surface and the second surface. The second surface has a plurality of ring-shaped grooves. Depths of the ring-shaped grooves are gradually decreased from a place close to a center of the LGP towards places close to the light incident surfaces. Each of the ring-shaped grooves has a first ring-shaped side wall surface and a second ring-shaped side wall surface. The second ring-shaped side wall surface is opposite to the first ring-shaped side wall surface and located between a geometry center of the ring-shaped groove and the first ring-shaped side wall surface. The first ring-shaped side wall surface is a tilted surface. In addition, a light source apparatus is also provided.

Abstract translation: 导光板（LGP）包括第一表面，第二表面和多个光入射表面。 第一表面是发光表面。 光入射表面连接第一表面和第二表面。 第二表面具有多个环形槽。 环形槽的深度从靠近LGP的中心的位置逐渐减小到靠近光入射表面的位置。 每个环形槽具有第一环形侧壁表面和第二环形侧壁表面。 第二环形侧壁表面与第一环形侧壁表面相对，并且位于环形槽的几何形状中心和第一环形侧壁表面之间。 第一环形侧壁表面是倾斜表面。 另外，还提供了光源装置。

公开(公告)号：US08491173B2

公开(公告)日：2013-07-23

申请号：US13295103

申请日：2011-11-14

Applicant: Sheng-Hung Lin ,  Chih-Ming Hu ,  Jung-Min Hwang

Inventor： Sheng-Hung Lin ,  Chih-Ming Hu ,  Jung-Min Hwang

IPC: F21V33/00

CPC classification number: G02F1/133603 ,  G02B6/0021 ,  G02B6/0028 ,  G02B6/0031 ,  G02B6/0068 ,  G02B6/0073 ,  G02F1/133615

Abstract: A light source module includes a transparent element, a plurality of light-emitting devices, and a plurality of light diffusion micro-structures. The transparent element includes a transparent substrate having a light exiting surface and a bottom surface opposite to the light exiting surface, a plurality of first notches, and a plurality of second notches. The first notches are sunken at the light exiting surface. There is a reflection surface in each of the first notches. The second notches are respectively opposite to the first notches and sunken at the bottom surface. The second notches respectively have a light incident curve-surface. The light-emitting devices are respectively disposed beside the light incident curve-surfaces. Each of the light-emitting devices has a light exiting surface capable of providing a light beam. The light exiting surface is not conformal to the light incident curve-surface. The light diffusion micro-structures are disposed on the bottom surface.

Abstract translation: 光源模块包括透明元件，多个发光器件和多个光扩散微结构。 透明元件包括具有光出射表面和与光出射表面相对的底表面的多个透明基底，多个第一凹口和多个第二凹口。 第一个凹口在光离开的表面凹陷。 每个第一个凹口中都有一个反射面。 第二凹口分别与第一凹口相对并在底表面下沉。 第二个凹口分别具有光入射曲面。 发光装置分别设置在光入射曲面旁边。 每个发光器件具有能够提供光束的光出射表面。 光出射表面不与光入射曲面保持一致。 光扩散微结构设置在底面上。

公开(公告)号：US08482063B2

公开(公告)日：2013-07-09

申请号：US13299446

申请日：2011-11-18

Applicant: An-Hung Lin ,  Hong-Ze Lin ,  Bo-Jui Huang ,  Wei-Shan Liao ,  Ting-Zhou Yan ,  Wei-Chun Chang ,  Chun-Yao Lee ,  Kun-Yi Chou

Inventor： An-Hung Lin ,  Hong-Ze Lin ,  Bo-Jui Huang ,  Wei-Shan Liao ,  Ting-Zhou Yan ,  Wei-Chun Chang ,  Chun-Yao Lee ,  Kun-Yi Chou

IPC: H01L29/66

CPC classification number: H01L29/0696 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/7816 ,  H01L29/7835

Abstract: A high voltage semiconductor device is provided. A first-polarity buried layer is formed in the substrate. A first high voltage second-polarity well region is located over the first-polarity buried layer. A second-polarity base region is disposed within the first high voltage second-polarity well region. A source region is disposed within the second-polarity base region. A high voltage deep first-polarity well region is located over the first-polarity buried layer and closely around the first high voltage second-polarity well region. A first-polarity drift region is disposed within the high voltage deep first-polarity well region. A gate structure is disposed over the substrate. A second high voltage second-polarity well region is located over the first-polarity buried layer and closely around the high voltage deep first-polarity well region. A deep first-polarity well region is located over the first-polarity buried layer and closely around the second high voltage second-polarity well region.

Abstract translation: 提供高压半导体器件。 在衬底中形成第一极性掩埋层。 第一高电压第二极性阱区位于第一极性掩埋层的上方。 第二极性基极区域设置在第一高电压第二极性阱区域内。 源极区域设置在第二极性基极区域内。 高电压深的第一极性极区位于第一极性埋层之上，紧邻第一高电压第二极性阱区。 第一极性漂移区域设置在高电压深第一极性阱区域内。 栅极结构设置在衬底上。 第二高电压第二极性阱区域位于第一极性掩埋层上方并且紧邻高电压深第一极性阱区域。 深第一极性阱区域位于第一极性掩埋层上并且紧邻第二高电压第二极性阱区域。

公开(公告)号：US08480284B2

公开(公告)日：2013-07-09

申请号：US13100291

申请日：2011-05-03

Applicant: Sheng-Hung Lin ,  Jung-Min Hwang ,  Shih-Yuan Yu ,  Ching-Yuan Chung

Inventor： Sheng-Hung Lin ,  Jung-Min Hwang ,  Shih-Yuan Yu ,  Ching-Yuan Chung

IPC: F21V8/00

CPC classification number: G02B6/0021 ,  G02B6/0038 ,  G02B6/0055 ,  G02B6/0068 ,  G02B6/0091

Abstract: A light guide unit including a light guide plate and a scattering reflective unit is provided. The light guide plate has a first surface, a second surface opposite to the first surface, and a light incident surface connecting the first surface and the second surface. The light incident surface includes a first recess and a second recess arranged in a sequence from the first surface to the second surface. An average radius of curvature of the first recess is less than an average radius of curvature of the second recess. The scattering reflective unit is disposed on the second surface. A light source module is also provided.

Abstract translation: 提供了包括导光板和散射反射单元的导光单元。 导光板具有第一表面，与第一表面相对的第二表面和连接第一表面和第二表面的光入射表面。 光入射表面包括从第一表面到第二表面的顺序排列的第一凹槽和第二凹槽。 第一凹部的平均曲率半径小于第二凹部的平均曲率半径。 散射反射单元设置在第二表面上。 还提供了光源模块。

公开(公告)号：US08471973B2

公开(公告)日：2013-06-25

申请号：US12788876

申请日：2010-05-27

Applicant: Hsiang-Lin Lin ,  Ching-Huan Lin ,  Chih-Hung Shih ,  Wei-Ming Huang ,  Chih-Hung Lin ,  Yu-Cheng Chen ,  Yi-Hui Li ,  Tsan-Chun Wang

Inventor： Hsiang-Lin Lin ,  Ching-Huan Lin ,  Chih-Hung Shih ,  Wei-Ming Huang ,  Chih-Hung Lin ,  Yu-Cheng Chen ,  Yi-Hui Li ,  Tsan-Chun Wang

IPC: G02F1/36

CPC classification number: G02F1/136209 ,  G02F1/136213 ,  G02F2001/13606 ,  G02F2201/40 ,  H01L27/1248 ,  H01L27/1255

Abstract: This invention in one aspect relates to a pixel structure. In one embodiment, the pixel structure includes a scan line formed on a substrate and a data line formed over the substrate defining a pixel area, a switch formed inside the pixel area on the substrate, a shielding electrode formed over the switch, a plane organic layer formed over the date line and the pixel area and having no overlapping with the shielding electrode, and a pixel electrode having a first portion and a second portion extending from the first portion, and formed over the shielding electrode and the plane organic layer in the pixel area, wherein the first portion is overlapped with the shielding electrode so as to define a storage capacitor therebetween, and the second portion overlays the plane organic layer and has no overlapping with the data line.

Abstract translation: 本发明在一个方面涉及像素结构。 在一个实施例中，像素结构包括形成在衬底上的扫描线和形成在限定像素区域的衬底上的数据线，形成在衬底上的像素区域内的开关，形成在开关上的屏蔽电极，有机平面 形成在日期线和像素区域上并且与屏蔽电极不重叠的像素电极，以及具有从第一部分延伸的第一部分和第二部分的像素电极，并且形成在屏蔽电极和平面有机层的上方 像素区域，其中第一部分与屏蔽电极重叠以便在其间限定存储电容器，并且第二部分覆盖平面有机层并且不与数据线重叠。

公开(公告)号：US20130143361A1

公开(公告)日：2013-06-06

申请号：US13309311

申请日：2011-12-01

Applicant: Wei-Hung Lin ,  Kuei-Wei Huang ,  Chih-Wei Lin ,  Chun-Cheng Lin ,  Ming-Da Cheng ,  Chung-Shi Liu

Inventor： Wei-Hung Lin ,  Kuei-Wei Huang ,  Chih-Wei Lin ,  Chun-Cheng Lin ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC: H01L21/60 ,  H01L23/12

CPC classification number: H01L21/6835 ,  H01L21/561 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/562 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L24/97 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05554 ,  H01L2224/05572 ,  H01L2224/05599 ,  H01L2224/11444 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13169 ,  H01L2224/14135 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/75754 ,  H01L2224/7698 ,  H01L2224/81001 ,  H01L2224/81136 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/81907 ,  H01L2224/83102 ,  H01L2224/9205 ,  H01L2224/92125 ,  H01L2224/95001 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/3841 ,  Y10T29/41 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2224/05552 ,  H01L2924/013

Abstract: Packaging process tools and systems, and packaging methods for semiconductor devices are disclosed. In one embodiment, a packaging process tool for semiconductor devices includes a mechanical structure for supporting package substrates or integrated circuit die during a packaging process for the integrated circuit die. The mechanical structure includes a low thermal conductivity material disposed thereon.

Abstract translation: 公开了用于半导体器件的封装加工工具和系统以及封装方法。 在一个实施例中，用于半导体器件的封装处理工具包括用于在集成电路管芯的封装工艺期间支撑封装衬底或集成电路管芯的机械结构。 机械结构包括设置在其上的低热导率材料。

公开(公告)号：US08456234B2

公开(公告)日：2013-06-04

申请号：US13152256

申请日：2011-06-02

Applicant: Wei-Hsiang Hung ,  Chia-Hung Lin

Inventor： Wei-Hsiang Hung ,  Chia-Hung Lin

IPC: H03G3/20 ,  H03F3/45

CPC classification number: H03F1/0261 ,  H03F3/45475 ,  H03F2203/45248

Abstract: A bias current control method for an operational amplifier is disclosed, which includes detecting a slew rate operating signal, determining signal period length of the slew rate operating signal to generate a determination signal, and generating a high bias modulation signal or a low bias modulation signal to the operational amplifier according to the determination signal and the slew rate operating signal.

Abstract translation: 公开了一种用于运算放大器的偏置电流控制方法，其包括检测转换速率操作信号，确定转换速率操作信号的信号周期长度以产生确定信号，以及产生高偏置调制信号或低偏置调制信号 根据确定信号和转换速率操作信号对运算放大器。

公开(公告)号：US20130126871A1

公开(公告)日：2013-05-23

申请号：US13402883

申请日：2012-02-23

Applicant: Chuan-Sheng Wei ,  Chau-Shiang Huang ,  Wu-Liu Tsai ,  Chih-Hung Lin ,  Maw-Song Chen

Inventor： Chuan-Sheng Wei ,  Chau-Shiang Huang ,  Wu-Liu Tsai ,  Chih-Hung Lin ,  Maw-Song Chen

IPC: H01L33/58

CPC classification number: H01L33/58 ,  G02F1/136213 ,  G02F1/136227 ,  H01L27/1255

Abstract: A pixel structure includes a first electrode on a substrate, a first insulation layer covering the first electrode, a gate located on the first insulation layer, a second electrode located on the first insulation layer above the first electrode, a second insulation layer covering the gate and the second electrode, a semiconductor layer located on the second insulation layer above the gate, a source and a drain that are located on the semiconductor layer, a third electrode, a third insulation layer, and a pixel electrode. The third electrode is located on the second insulation layer above the second electrode and electrically connected to the first electrode. The third insulation layer covers the source, the drain, and the third electrode. The pixel electrode is located on the third insulation layer and electrically connected to the drain.

Abstract translation: 像素结构包括在基板上的第一电极，覆盖第一电极的第一绝缘层，位于第一绝缘层上的栅极，位于第一电极上方的第一绝缘层上的第二电极，覆盖栅极的第二绝缘层 并且第二电极，位于栅极上方的第二绝缘层上的半导体层，位于半导体层上的源极和漏极，第三电极，第三绝缘层和像素电极。 第三电极位于第二电极上方的第二绝缘层上并与第一电极电连接。 第三绝缘层覆盖源极，漏极和第三电极。 像素电极位于第三绝缘层上并与漏极电连接。