公开(公告)号：US20090124047A1

公开(公告)日：2009-05-14

申请号：US12353549

申请日：2009-01-14

Applicant: James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Stephen E. Luce ,  Richard J. Rassel ,  Edmund J. Sprogis

Inventor： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Stephen E. Luce ,  Richard J. Rassel ,  Edmund J. Sprogis

IPC: H01L21/70

CPC classification number: H01L27/14618 ,  H01L25/0657 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/13091 ,  H01L2924/15151 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An imaging system for use in a digital camera or cell phone utilizes one chip for logic and one chip for image processing. The chips are interconnected using around-the-edge or through via conductors extending from bond pads on the active surface of the imaging chip to backside metallurgy on the imaging chip. The backside metallurgy of the imaging chip is connected to metallurgy on the active surface of the logic chip using an array of solder bumps in BGA fashion. The interconnection arrangement provides a CSP which matches the space constraints of a cell phone, for example. The arrangement also utilizes minimal wire lengths for reduced noise. Connection of the CSP to a carrier package may be either by conductive through vias or wire bonding. The CSP is such that the imaging chip may readily be mounted across an aperture in the wall of a cell phone, for example, so as to expose the light sensitive pixels on the active surface of said imaging chip to light.

Abstract translation: 用于数码相机或手机的成像系统利用一个芯片用于逻辑和一个芯片用于图像处理。 这些芯片使用围绕成像芯片的有源表面上的接合焊盘的边缘或通孔导体互连，从而在成像芯片上进行背面冶金。 成像芯片的背面冶金采用BGA焊料凸块阵列与逻辑芯片的有源表面上的冶金连接。 互连装置提供例如与手机的空间限制相匹配的CSP。 该布置还利用最小的线长度来降低噪声。 将CSP连接到载体封装可以通过通孔或引线键合导电。 CSP使得成像芯片可以容易地安装在例如手机的壁中的孔之间，以便将所述成像芯片的有效表面上的光敏像素曝光到光。

公开(公告)号：US20090108347A1

公开(公告)日：2009-04-30

申请号：US11924650

申请日：2007-10-26

Applicant: James W. Adkisson ,  Natalie B. Feilchenfeld ,  Jeffrey P. Gambino ,  Benjamin T. Voegeli ,  Michael J. Zierak

Inventor： James W. Adkisson ,  Natalie B. Feilchenfeld ,  Jeffrey P. Gambino ,  Benjamin T. Voegeli ,  Michael J. Zierak

IPC: H01L29/78

CPC classification number: H01L29/7835 ,  H01L29/1045 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/512 ,  H01L29/66659

Abstract: A gate stack comprising a uniform thickness gate dielectric, a gate electrode, and an oxygen-diffusion-resistant gate cap is formed on a semiconductor substrate. Thermal oxidation is performed only on the drain side of the gate electrode, while the source side is protected from thermal oxidation. A thermal oxide on the drain side sidewall of the gate electrode is integrally formed with a graded thickness silicon oxide containing gate dielectric, of which the thickness monotonically increases from the source side to the drain side. The thickness profile may be self-aligned to the drain side edge of the gate electrode, or may have a portion with a self-limiting thickness. The graded thickness profile may be advantageously used to form a lateral diffusion metal oxide semiconductor field effect transistor providing an enhanced performance.

Abstract translation: 在半导体基板上形成包括均匀厚度的栅极电介质，栅电极和耐氧扩散栅极盖的栅极堆叠。 仅在栅电极的漏极侧进行热氧化，同时防止源极侧受热氧化。 栅电极的漏极侧壁上的热氧化物与层状厚度的含氧化硅的栅极电介质整体形成，其厚度从源极侧向漏极侧单调增加。 厚度分布可以与栅电极的漏极侧边缘自对准，或者可以具有自限制厚度的部分。 梯度厚度分布可以有利地用于形成提供增强性能的横向扩散金属氧化物半导体场效应晶体管。

公开(公告)号：US20090090983A1

公开(公告)日：2009-04-09

申请号：US11866594

申请日：2007-10-03

Applicant: James W. Adkisson ,  Jeffrey P. Gambino ,  Edward J. Nowak ,  Steven H. Voldman ,  Michael J. Zierak

Inventor： James W. Adkisson ,  Jeffrey P. Gambino ,  Edward J. Nowak ,  Steven H. Voldman ,  Michael J. Zierak

IPC: H01L29/78

CPC classification number: H01L29/4983 ,  H01L29/41725 ,  H01L29/41775 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/7835

Abstract: A transistor has a substrate having a channel region and source and drain regions within the substrate on opposite sides of the channel region. The structure includes a gate oxide above the channel region of the substrate and a gate conductor above the gate oxide. The polysilicon gate conductor comprises a source side positioned toward the source and a drain side positioned toward the drain. The source side comprises a first concentration of conductive doping and the drain side comprises a second concentration of the conductive doping that is less than the first concentration.

Abstract translation: 晶体管具有衬底，该衬底具有在沟道区域的相对侧上的衬底内的沟道区和源极和漏极区。 该结构包括在衬底的沟道区上方的栅极氧化物和栅极氧化物上方的栅极导体。 多晶硅栅极导体包括位于源极侧的源极侧和朝向漏极定位的漏极侧。 源侧包括第一浓度的导电掺杂，而漏极侧包括小于第一浓度的导电掺杂的第二浓度。

公开(公告)号：US20090045502A1

公开(公告)日：2009-02-19

申请号：US11838917

申请日：2007-08-15

Applicant: James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Edmund J. Sprogis

Inventor： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Edmund J. Sprogis

IPC: H01L23/488 ,  H01L21/60

CPC classification number: H01L23/3157 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L24/82 ,  H01L2224/0401 ,  H01L2224/16 ,  H01L2924/10253 ,  H01L2924/12043 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A semiconductor chip scale package formed with through-vias, which can be either isolated or electrically connected to a substrate, and a method of producing the semiconductor chip scale package with through-vias, which can be isolated or electrically connected to the substrate.

Abstract translation: 形成有可以与衬底隔离或电连接的通孔形成的半导体芯片级封装，以及可以隔离或电连接到衬底的具有通孔的半导体芯片级封装的制造方法。

公开(公告)号：US07491992B2

公开(公告)日：2009-02-17

申请号：US11619024

申请日：2007-01-02

Applicant: James W. Adkisson ,  John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Richard J. Rassel ,  Jeffrey P. Gambino

Inventor： James W. Adkisson ,  John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Richard J. Rassel ,  Jeffrey P. Gambino

IPC: H01L31/62 ,  H01L31/113

CPC classification number: H01L27/14609 ,  H01L27/1463 ,  H01L27/14641 ,  H01L27/14643 ,  H01L31/035281

Abstract: A structure (and method for forming the same) for an image sensor cell. The method includes providing a semiconductor substrate. Then, a charge collection well is formed in the semiconductor substrate, the charge collection well comprising dopants of a first doping polarity. Next, a surface pinning layer is formed in the charge collection well, the surface pinning layer comprising dopants of a second doping polarity opposite to the first doping polarity. Then, an electrically conductive push electrode is formed in direct physical contact with the surface pinning layer but not in direct physical contact with the charge collection well. Then, a transfer transistor is formed on the semiconductor substrate. The transfer transistor includes first and second source/drain regions and a channel region. The first and second source/drain regions comprise dopants of the first doping polarity. The first source/drain region is in direct physical contact with the charge collection well.

Abstract translation: 用于图像传感器单元的结构（及其形成方法）。 该方法包括提供半导体衬底。 然后，在半导体衬底中形成电荷收集阱，电荷收集阱包含第一掺杂极性的掺杂剂。 接下来，在电荷收集阱中形成表面钉扎层，表面钉扎层包括与第一掺杂极性相反的第二掺杂极性的掺杂剂。 然后，导电的推动电极形成为与表面钉扎层直接物理接触，但不与电荷收集阱直接物理接触。 然后，在半导体衬底上形成传输晶体管。 传输晶体管包括第一和第二源极/漏极区域和沟道区域。 第一和第二源/漏区包括第一掺杂极性的掺杂剂。 第一源极/漏极区域与电荷收集阱直接物理接触。

公开(公告)号：US20090001427A1

公开(公告)日：2009-01-01

申请号：US11770843

申请日：2007-06-29

Applicant: James W. Adkisson ,  John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Mark D. Jaffe

Inventor： James W. Adkisson ,  John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Mark D. Jaffe

IPC: H01L27/148 ,  H01L31/113 ,  H01L31/18

CPC classification number: H01L27/14689 ,  H01L27/14609 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/14643

Abstract: A pixel sensor structure, method of manufacture and method of operating. Disclosed is a buffer pixel cell comprising a barrier region for preventing stray charge carriers from arriving at a dark current correction pixel cell. The buffer pixel cell is located in the vicinity of the dark current correction pixel cell and the buffer pixel cell resembles an active pixel cell. Thus, an environment surrounding the dark current correction pixel cell is similar to the environment surrounding an active pixel cell.

Abstract translation: 像素传感器结构，制造方法和操作方法。 公开了一种缓冲像素单元，其包括用于防止杂散电荷载流子到达暗电流校正像素单元的阻挡区域。 缓冲像素单元位于暗电流校正像素单元附近，并且缓冲像素单元类似于有源像素单元。 因此，围绕暗电流校正像素单元的环境与有源像素单元周围的环境相似。

公开(公告)号：US20080088014A1

公开(公告)日：2008-04-17

申请号：US11528227

申请日：2006-09-26

Applicant: James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Stephen E. Luce ,  Richard J. Rassel ,  Edmund J. Sprogis

Inventor： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Stephen E. Luce ,  Richard J. Rassel ,  Edmund J. Sprogis

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L27/14618 ,  H01L25/0657 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/13091 ,  H01L2924/15151 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An imaging system for use in a digital camera or cell phone utilizes one chip for logic and one chip for image processing. The chips are interconnected using around-the-edge or through via conductors extending from bond pads on the active surface of the imaging chip to backside metallurgy on the imaging chip. The backside metallurgy of the imaging chip is connected to metallurgy on the active surface of the logic chip using an array of solder bumps in BGA fashion. The interconnection arrangement provides a CSP which matches the space constraints of a cell phone, for example. The arrangement also utilizes minimal wire lengths for reduced noise. Connection of the CSP to a carrier package may be either by conductive through vias or wire bonding. The CSP is such that the imaging chip may readily be mounted across an aperture in the wall of a cell phone, for example, so as to expose the light sensitive pixels on the active surface of said imaging chip to light.

Abstract translation: 用于数码相机或手机的成像系统利用一个芯片用于逻辑和一个芯片用于图像处理。 这些芯片使用围绕成像芯片的有源表面上的接合焊盘的边缘或通孔导体互连，从而在成像芯片上进行背面冶金。 成像芯片的背面冶金采用BGA焊料凸块阵列与逻辑芯片的有源表面上的冶金连接。 互连装置提供例如与手机的空间限制相匹配的CSP。 该布置还利用最小的线长度来降低噪声。 将CSP连接到载体封装可以通过通孔或引线键合导电。 CSP使得成像芯片可以容易地安装在例如手机的壁中的孔之间，以便将所述成像芯片的有效表面上的光敏像素曝光到光。

公开(公告)号：US07193289B2

公开(公告)日：2007-03-20

申请号：US10904807

申请日：2004-11-30

Applicant: James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Anthony K. Stamper

Inventor： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Anthony K. Stamper

IPC: H01L27/14

CPC classification number: H01L27/14685 ,  H01L21/76819 ,  H01L21/76834 ,  H01L21/76838 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/14687

Abstract: An image sensor array and method of fabrication wherein the sensor includes Copper (Cu) metallization levels allowing for incorporation of a thinner interlevel dielectric stack with improved thickness uniformity to result in a pixel array exhibiting increased light sensitivity. In the sensor array, each Cu metallization level includes a Cu metal wire structure formed at locations between each array pixel and, a barrier material layer is formed on top each Cu metal wire structure that traverses the pixel optical path. By implementing a single mask or self-aligned mask methodology, a single etch is conducted to completely remove the interlevel dielectric and barrier layers that traverse the optical path. The etched opening is then refilled with dielectric material. Prior to depositing the refill dielectric, a layer of either reflective or absorptive material is formed along the sidewalls of the etched opening to improve sensitivity of the pixels by either reflecting light to the underlying photodiode or by eliminating light reflections.

Abstract translation: 一种图像传感器阵列和制造方法，其中传感器包括铜（Cu）金属化水平，允许结合更薄的层间电介质叠层，改进的厚度均匀性，以产生呈现增加的光敏度的像素阵列。 在传感器阵列中，每个Cu金属化层包括在每个阵列像素之间的位置处形成的Cu金属线结构，并且阻挡材料层形成在穿过像素光路的每个Cu金属线结构上。 通过实现单掩模或自对准掩模方法，进行单次蚀刻以完全去除穿过光路的层间电介质层和阻挡层。 然后将蚀刻的开口用电介质材料重新填充。 在沉积再充填电介质之前，沿蚀刻开口的侧壁形成反射或吸收材料层，以通过将光反射到下面的光电二极管或通过消除光反射来提高像素的灵敏度。

公开(公告)号：US06472258B1

公开(公告)日：2002-10-29

申请号：US09711725

申请日：2000-11-13

Applicant: James W. Adkisson ,  Paul D. Agnello ,  Arne W. Ballantine ,  Rama Divakaruni ,  Erin C. Jones ,  Jed H. Rankin

Inventor： James W. Adkisson ,  Paul D. Agnello ,  Arne W. Ballantine ,  Rama Divakaruni ,  Erin C. Jones ,  Jed H. Rankin

IPC: H01L2130

CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66818

Abstract: A field effect transistor is formed with a sub-lithographic conduction channel and a dual gate which is formed by a simple process by starting with a silicon-on-insulator wafer, allowing most etching processes to use the buried oxide as an etch stop. Low resistivity of the gate, source and drain is achieved by silicide sidewalls or liners while low gate to junction capacitance is achieved by recessing the silicide and polysilicon dual gate structure from the source and drain region edges.

Abstract translation: 场效应晶体管由亚光刻导电沟道和双栅极形成，该双栅极通过简单的工艺由绝缘体上硅晶片开始形成，允许大多数蚀刻工艺使用掩埋氧化物作为蚀刻停止。 通过硅化物侧壁或衬垫实现栅极，源极和漏极的低电阻率，而通过从源极和漏极区域边缘凹陷硅化物和多晶硅双栅极结构来实现低栅极至结电容。

公开(公告)号：US06445194B1

公开(公告)日：2002-09-03

申请号：US09788084

申请日：2001-02-16

Applicant: James W. Adkisson ,  Arne W. Ballantine ,  Ralph W. Young

Inventor： James W. Adkisson ,  Arne W. Ballantine ,  Ralph W. Young

IPC: G01R2726

CPC classification number: H01L22/34 ,  G11C2029/0403 ,  H01L21/31612

Abstract: The invention provides a monitor wafer and a method using the wafer to measure the conformality of dielectric films and in particular, for measuring the sidewall deposition thickness of dielectric films.

Abstract translation: 本发明提供一种监测晶片和使用晶片来测量介电膜的共形性的方法，特别是用于测量电介质膜的侧壁沉积厚度。