中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

80 records (took 0.022 seconds)

    Vaporization and ionization of metals for use in semiconductor processing
    62.
    发明授权
    Vaporization and ionization of metals for use in semiconductor processing 失效
    用于半导体加工的金属的蒸发和电离

    公开(公告)号：US07084408B1

    公开(公告)日：2006-08-01

    申请号：US10697507

    申请日：2003-10-29

    Applicant: James Kimball ,  Sheldon Aronowitz

    Inventor： James Kimball ,  Sheldon Aronowitz

    IPC: H01J27/00 ,  H01J37/08 ,  G21K5/10

    CPC classification number: H01J27/04 ,  C23C14/228 ,  C23C14/32 ,  C23C14/48

    Abstract: Techniques for vaporizing and handling a vaporized metallic element or metallic element salt with a heated inert carrier gas for further processing. The vaporized metallic element or salt is carried by an inert carrier gas heated to the same temperature as the vaporizing temperature to a heated processing chamber. The metal or salt vapor may be ionized (and implanted) or deposited on substrates. Apparatus for accomplishing these techniques, which include carrier gas heating chambers and heated processing chambers are also provided.

    Abstract translation: 用加热的惰性载气汽化和处理蒸发的金属元素或金属元素盐进行进一步处理的技术。 蒸发的金属元素或盐由加热至与蒸发温度相同的温度的惰性载气携带到加热的处理室。 金属或盐蒸气可以离子化（和注入）或沉积在基底上。 还提供了用于实现这些技术的装置，其包括载气加热室和加热处理室。

    Memory device having an electron trapping layer in a high-K dielectric gate stack
    64.
    发明授权
    Memory device having an electron trapping layer in a high-K dielectric gate stack 失效
    在高K电介质栅叠层中具有电子俘获层的存储器件

    公开(公告)号：US06989565B1

    公开(公告)日：2006-01-24

    申请号：US10698169

    申请日：2003-10-31

    Applicant: Sheldon Aronowitz ,  Vladimir Zubkov ,  Grace S. Sun

    Inventor： Sheldon Aronowitz ,  Vladimir Zubkov ,  Grace S. Sun

    IPC: H01L29/792

    CPC classification number: H01L29/517 ,  H01L21/28185 ,  H01L21/28194 ,  H01L29/513 ,  H01L29/78

    Abstract: An improved semiconductor memory structure and methods for its fabrication are disclosed. The memory structure includes a semiconductor substrate having a dielectric stack formed over a channel region of a semiconductor substrate. The dielectric stack includes a layer of electron trapping material that operates as a charge storage center for memory devices. A gate electrode is connected with the top of the dielectric stack. In various embodiments the electron trapping material forms a greater or lesser portion of the dielectric stack. The invention includes a method embodiment for forming such a memory device.

    Abstract translation: 公开了一种改进的半导体存储器结构及其制造方法。 存储器结构包括具有在半导体衬底的沟道区上形成的电介质叠层的半导体衬底。 电介质堆叠包括作为存储器件的电荷存储中心工作的电子俘获材料层。 栅电极与电介质叠层的顶部连接。 在各种实施例中，电子捕获材料形成介电叠层的更大或更小部分。 本发明包括用于形成这种存储器件的方法实施例。

    Calcium doped polysilicon gate electrodes
    65.
    发明授权
    Calcium doped polysilicon gate electrodes 失效
    掺杂多晶硅的栅电极

    公开(公告)号：US06930362B1

    公开(公告)日：2005-08-16

    申请号：US10698167

    申请日：2003-10-30

    Applicant: Mohammad R. Mirabedini ,  Grace S. Sun ,  Sheldon Aronowitz

    Inventor： Mohammad R. Mirabedini ,  Grace S. Sun ,  Sheldon Aronowitz

    IPC: H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L29/76 ,  H01L29/78

    CPC classification number: H01L29/6656 ,  H01L21/265 ,  H01L21/28035 ,  H01L29/4925 ,  H01L29/78

    Abstract: A calcium doped polysilicon gate electrodes for PMOS containing semiconductor devices. The calcium doped PMOS gate electrodes reduce migration of the boron dopant out of the gate electrode, through the gate dielectric and into the substrate thereby reducing the boron penetration problem increasingly encountered with smaller device size regimes and their thinner gate dielectrics. Calcium doping of the gate electrode may be achieved by a variety of techniques. It is further believed that the calcium doping may improve the boron dopant activation in the gate electrode, thereby further improving performance.

    Abstract translation: 用于含PMOS半导体器件的掺杂钙的多晶硅栅电极。 掺杂钙的PMOS栅电极减少了硼掺杂剂离开栅极电极的迁移，通过栅极电介质并进入衬底中，从而减小了越来越多的器件尺寸状态和其更薄的栅极电介质越来越多地遇到的硼渗透问题。 栅电极的钙掺杂可以通过各种技术来实现。 进一步认为钙掺杂可以改善栅电极中的硼掺杂剂活化，从而进一步提高性能。

    Process for forming high dielectric constant gate dielectric for integrated circuit structure
    67.
    发明授权
    Process for forming high dielectric constant gate dielectric for integrated circuit structure 有权
    用于形成用于集成电路结构的高介电常数栅极电介质的工艺

    公开(公告)号：US06511925B1

    公开(公告)日：2003-01-28

    申请号：US10033164

    申请日：2001-10-19

    Applicant: Sheldon Aronowitz ,  Vladimir Zubkov ,  Helmut Puchner

    Inventor： Sheldon Aronowitz ,  Vladimir Zubkov ,  Helmut Puchner

    IPC: H01L218238

    CPC classification number: H01L21/28185 ,  H01L21/2236 ,  H01L21/265 ,  H01L29/517

    Abstract: In accordance with the invention a high-k gate dielectric is formed by the steps of first forming a silicon oxide layer over a silicon substrate and then exposing the silicon oxide to a flux of low energy plasma containing metal ions which, when inserted into silicon oxide, form a high-k dielectric material suitable for use as a high-k gate dielectric. In one embodiment, the silicon oxide is exposed to a first plasma containing a first species of metal ions and then to a plasma of another species of metal ions which, when inserted into the silicon oxide with the metal ions in the first plasma, further increase the dielectric constant of the silicon oxide.

    Abstract translation: 根据本发明，通过以下步骤形成高k栅极电介质：首先在硅衬底上形成氧化硅层，然后将氧化硅暴露于含有金属离子的低能量等离子体的焊剂中，该金属离子当插入到氧化硅 形成适合用作高k栅极电介质的高k电介质材料。 在一个实施例中，氧化硅暴露于含有第一种金属离子的第一等离子体，然后暴露于另一种金属离子的等离子体，当等离子体中的金属离子插入到氧化硅中时，其进一步增加 氧化硅的介电常数。

    FETs having lightly doped drain regions that are shaped with counter and noncounter dorant elements
    68.
    发明授权
    FETs having lightly doped drain regions that are shaped with counter and noncounter dorant elements 失效
    具有轻掺杂漏极区域的FET，其被形成有反向和不对称的多个元件

    公开(公告)号：US06180470B2

    公开(公告)日：2001-01-30

    申请号：US08770046

    申请日：1996-12-19

    Applicant: Sheldon Aronowitz ,  Laique Khan ,  James Kimball

    Inventor： Sheldon Aronowitz ,  Laique Khan ,  James Kimball

    IPC: H01L21336

    CPC classification number: H01L29/6659 ,  H01L21/2652 ,  H01L21/26586 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/7833 ,  Y10S438/925

    Abstract: Lifetime of a short-channel NMOS device is increased by modifying distributions of electrically active LDD dopant at boundaries of the device's LDD regions. The LDD dopant distributions are modified by implanting counter-dopants at the boundaries of the LDD regions. Group III counter-dopants such as boron and group IV elements such as silicon alter activation properties of the LDD dopant. The dopant distributions are modified at the device's n-junctions to reduce the maximum electric field displacement at an interface defined by the device's gate and substrate. The dopant distributions can be further modified to shape the n-junctions such that hot carriers are injected away from the gate.

    Abstract translation: 通过修改器件的LDD区域边界处的电活性LDD掺杂剂的分布来增加短沟道NMOS器件的寿命。 通过在LDD区域的边界处注入反掺杂剂来修改LDD掺杂剂分布。 III族反掺杂剂如硼和IV族元素如硅改变LDD掺杂剂的活化性质。 掺杂剂分布在器件的n结处修改，以减少由器件的栅极和衬底限定的界面处的最大电场位移。 可以进一步修改掺杂剂分布以使n结成形，使得热载流子从栅极注入。

    Composite semiconductor gate dielectrics
    69.
    发明授权
    Composite semiconductor gate dielectrics 失效
    复合半导体栅极电介质

    公开(公告)号：US6087229A

    公开(公告)日：2000-07-11

    申请号：US37588

    申请日：1998-03-09

    Applicant: Sheldon Aronowitz ,  David Chan ,  James Kimball ,  David Lee ,  John Haywood ,  Valeriy Sukharev

    Inventor： Sheldon Aronowitz ,  David Chan ,  James Kimball ,  David Lee ,  John Haywood ,  Valeriy Sukharev

    IPC: H01L21/28 ,  H01L29/51 ,  H01L21/336

    CPC classification number: H01L21/28194 ,  H01L21/0214 ,  H01L21/02238 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/02326 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/518

    Abstract: Provided are methods for fabricating hardened composite thin layer gate dielectrics. According to preferred embodiments of the present invention, composite gate dielectrics may be produced as bilayers having oyxnitride portions with nitrogen contents above 10 atomic percent, while avoiding the drawbacks of prior art nitridization methods. In one aspect of the present invention, a hardened composite thin layer gate dielectric may be formed by deposition of a very thin silicon layer on a very thin oxide layer on a silicon substrate, followed by low energy plasma nitridization and subsequent oxidation of the thin silicon layer. In another aspect of the invention, low energy plasma nitridization of a thin oxide layer formed on a silicon substrate may be followed by deposition of a very thin silicon layer and subsequent oxidation, or additional low energy plasma nitridization and then oxidation, of the thin silicon layer.

    Abstract translation: 提供制造硬化复合薄层栅极电介质的方法。 根据本发明的优选实施方案，复合栅极电介质可以制备成具有氮含量高于10原子百分比的氮氧化物部分的双层，同时避免了现有技术氮化方法的缺点。 在本发明的一个方面，可以通过在硅衬底上的非常薄的氧化物层上沉积非常薄的硅层，随后进行低能量等离子体氮化和随后的薄硅氧化来形成硬化的复合薄层栅极电介质 层。 在本发明的另一方面，形成在硅衬底上的薄氧化物层的低能量等离子体氮化可以随后沉积非常薄的硅层，然后沉积薄硅层，随后进行氧化或另外的低能量等离子体氮化，然后氧化 层。

Patent Agency Ranking