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公开(公告)号：US20170194229A1
公开(公告)日：2017-07-06
申请号：US14985256
申请日：2015-12-30
发明人： Wanbing Yi , Mahesh Bhatkar , Chin Chuan Neo , Juan Boon Tan
IPC分类号： H01L23/31 , H01L23/29 , H01L23/532 , H01L21/56 , H01L21/768 , H01L23/528
CPC分类号： H01L23/3192 , H01L21/56 , H01L21/76804 , H01L21/76816 , H01L21/76877 , H01L23/291 , H01L23/528 , H01L23/53214 , H01L23/53228
摘要： A method for fabricating an integrated circuit includes forming a first opening in an upper dielectric layer, the first opening having a first width, forming a second opening in a lower dielectric layer, the lower dielectric layer being below the upper dielectric layer, the second opening having a second width that is narrower than the first width, the second opening being substantially centered underneath the first opening so as to form a stepped via structure, conformally depositing an aluminum material layer in the stepped via structure and over the upper dielectric layer, and forming a passivation layer over the aluminum material layer.
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62.发明授权公开(公告)号：US09613897B2
公开(公告)日：2017-04-04
申请号：US14537942
申请日：2014-11-11
发明人： Mahesh Bhatkar , Lulu Peng , Wanbing Yi , Juan Boon Tan , Luke England
CPC分类号： H01L23/5227 , H01F1/14 , H01F1/14708 , H01F1/14766 , H01F17/0013 , H01F27/24 , H01F27/2804 , H01F41/046 , H01F2017/0066 , H01F2027/2809 , H01L28/10 , H01L2924/0002 , H01L2924/00
摘要： Magnetic core inductors implemented on integrated circuits and methods for fabricating such magnetic core inductors are disclosed. An exemplary magnetic core inductor includes a bottom magnetic plate that includes a center portion and first, second, third, and fourth extension portions extending from the center portion. The exemplary magnetic core inductor includes an interlayer dielectric layer disposed over the bottom magnetic plate, and within the interlayer dielectric layer, first, second, third, and fourth via trenches extending above a respective one of the first, second, third, and fourth extension portions, and a fifth via trench extending above the center portion. The magnetic core inductor further includes a stacked-ring inductor coil including a plurality of inductor rings surrounding the fifth via trench and a top magnetic plate including a center portion and first, second, third, and fourth extension portions extending from the center portion.
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公开(公告)号：US09520371B2
公开(公告)日：2016-12-13
申请号：US14525154
申请日：2014-10-27
发明人： Benfu Lin , Wanbing Yi , Wei Lu , Alex See , Juan Boon Tan
IPC分类号： H01L23/00 , H01L21/3105 , H01L21/768 , H01L23/522 , H01L23/528 , H01L23/31 , H01L23/532
CPC分类号： H01L24/05 , H01L21/31051 , H01L21/76807 , H01L21/76877 , H01L23/3114 , H01L23/3192 , H01L23/53214 , H01L23/53228 , H01L23/53295 , H01L24/02 , H01L24/03 , H01L24/48 , H01L24/85 , H01L24/94 , H01L2224/02166 , H01L2224/023 , H01L2224/0345 , H01L2224/03462 , H01L2224/03614 , H01L2224/03616 , H01L2224/0391 , H01L2224/04042 , H01L2224/05025 , H01L2224/05546 , H01L2224/05567 , H01L2224/05573 , H01L2224/05624 , H01L2224/05647 , H01L2224/48247 , H01L2224/94 , H01L2924/00014 , H01L2924/06 , H01L2924/07025 , H01L2924/3512 , H01L2924/35121 , H01L2224/03 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Devices and methods for forming a device are presented. The method includes providing a substrate having circuit component and a dielectric layer over the substrate. The dielectric layer includes a plurality of inter level dielectric (ILD) layers and the uppermost dielectric layer includes at least one interconnect. A pad dielectric layer is provided over the uppermost ILD layer. A pad interconnect for receiving a wire bond is formed in the pad dielectric layer. The pad interconnect is coupled to the at least one interconnect of the uppermost ILD layer. A top surface of the pad dielectric layer is substantially coplanar with a top surface of the pad interconnect. A passivation layer is formed over the pad dielectric layer.
摘要翻译： 提出了用于形成装置的装置和方法。 该方法包括在衬底上提供具有电路部件和电介质层的衬底。 电介质层包括多个层间介电层（ILD）层，最上面的介电层包括至少一个互连。 衬垫介电层设置在最上面的ILD层之上。 在焊盘介电层中形成用于接收引线接合的焊盘互连。 焊盘互连耦合到最上面的ILD层的至少一个互连。 焊盘介电层的顶表面与焊盘互连的顶表面基本共面。 在焊盘介电层上形成钝化层。
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64.发明授权Integrated circuit structures with spin torque transfer magnetic random access memory ultilizing aluminum metallization layers and methods for fabricating the same 有权具有自旋扭矩传递磁性随机存取存储器的集成电路结构，其具有极高的铝金属化层及其制造方法公开(公告)号：US09490423B2
公开(公告)日：2016-11-08
申请号：US14537955
申请日：2014-11-11
发明人： Juan Boon Tan , Wanbing Yi , Danny Pak-Chum Shum
CPC分类号： H01L43/12 , G11C11/15 , G11C11/16 , G11C11/161 , H01L27/222 , H01L43/02 , H01L43/08 , H01L43/10
摘要： STT-MRAM integrated circuits employing aluminum metallization layers and methods for fabricating the same are disclosed. A method for fabricating an integrated circuit includes forming a first metallization layer including an aluminum material, forming a magnetic tunnel junction (MTJ) structure over the first metallization layer, and forming an encapsulation layer over the MTJ structure and over the first metallization layer. The method further includes etching the encapsulation layer and the first metallization layer to form an encapsulation segment overlying a first metal line, forming a contact plug to the MTJ structure, and forming a second metal line including an aluminum material over the contact plug.
摘要翻译： 公开了采用铝金属化层的STT-MRAM集成电路及其制造方法。 一种用于制造集成电路的方法包括：形成包括铝材料的第一金属化层，在第一金属化层上形成磁隧道结（MTJ）结构，以及在MTJ结构之上和第一金属化层之上形成封装层。 该方法还包括蚀刻封装层和第一金属化层以形成覆盖第一金属线的封装段，形成到MTJ结构的接触塞，以及在接触插塞上形成包括铝材料的第二金属线。
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公开(公告)号：US09240374B2
公开(公告)日：2016-01-19
申请号：US14142934
申请日：2013-12-30
发明人： Wei Shao , Wanbing Yi , Shunqiang Gong , Chao Zhu , Juan Boon Tan
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L23/522 , H01L21/768 , H01L23/532
CPC分类号： H01L23/5226 , H01L21/76807 , H01L21/76814 , H01L21/76846 , H01L21/76888 , H01L23/53214 , H01L23/53228 , H01L23/53257 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor device and method for forming a semiconductor device are presented. The method includes providing a substrate prepared with intermediate dielectric layer having interconnect levels. The interconnect levels include M1 to MX metal levels, where 1 is the lowest level and X corresponds to a number of metal level. The metal level MX includes a metal pad having an oxidized portion. An upper level having an upper dielectric layer is formed over the dielectric layer having MX. The upper dielectric layer includes a plurality of via contacts over the metal pad and a metal line over the via contacts. The oxidized portion remains within the metal pad and prevents punch through between MX and its adjacent underlying metal level MX-1.
摘要翻译： 本发明提供半导体装置及其制造方法。 该方法包括提供用具有互连级别的中间介电层制备的衬底。 互连级别包括M1到MX金属级别，其中1是最低级别，X对应于多个金属级别。 金属层MX包括具有氧化部分的金属垫。 在具有MX的电介质层上形成具有上电介质层的上层。 上介电层包括在金属焊盘上方的多个通孔触点和通孔触点上方的金属线。 氧化部分保留在金属垫内，并防止MX与其相邻的下层金属级MX-1之间的穿孔。
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公开(公告)号：US12009326B2
公开(公告)日：2024-06-11
申请号：US17584507
申请日：2022-01-26
发明人： Hari Balan , Juan Boon Tan , Ramasamy Chockalingam , Wanbing Yi
IPC分类号： H01L23/00 , H01L23/528 , H01L25/00 , H01L25/065
CPC分类号： H01L24/08 , H01L23/5286 , H01L24/80 , H01L25/0657 , H01L25/50 , H01L2224/08145 , H01L2224/80895 , H01L2224/80896 , H01L2924/1437
摘要： Structures for a static random access memory bit cell and methods of forming a structure for a static random access memory bit cell. The structure includes a first field-effect transistor on a first substrate and a second field-effect transistor on a second substrate. The first field-effect transistor includes a first gate, and the second field-effect transistor includes a second gate. The structure further includes a first interconnect structure on the first substrate and a second interconnect structure on the second substrate. The first interconnect structure includes a first metal feature connected to the first gate, and the first metal feature has a first surface. The second interconnect structure includes a second metal feature connected to the second gate, and the second metal feature has a second surface that is connected to the first surface of the first metal feature.
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公开(公告)号：US11978510B2
公开(公告)日：2024-05-07
申请号：US17387964
申请日：2021-07-28
发明人： Curtis Chun-I Hsieh , Wei-Hui Hsu , Wanbing Yi , Yi Jiang , Kai Kang , Juan Boon Tan
CPC分类号： G11C13/004 , H10B63/30 , H10N70/063 , G11C2013/0045 , G11C2013/0054 , G11C2213/79
摘要： The present disclosure generally relates to memory devices and methods of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices incorporating reference cells for achieving high sensing yield. The present disclosure provides a memory device including a main cell structure including a switching element arranged between a pair of conductors, and a reference cell structure electrically coupled to the main cell structure. The reference cell structure includes a switching element arranged between a pair of conductors, in which the switching element of the reference cell structure has a dimension that is different from a dimension of the switching element of the main cell structure.
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68.发明公开公开(公告)号：US20230411208A1
公开(公告)日：2023-12-21
申请号：US17807905
申请日：2022-06-21
发明人： Wensheng Deng , Kemao Lin , Curtis Chun-I Hsieh , Wanbing Yi , Liu Xinfu , Rui Tze Toh , Yanxia Shao , Shucheng Yin , Jason Kin Wei Wong , Yung Fu Chong
IPC分类号： H01L21/768 , H01L23/522
CPC分类号： H01L21/7682 , H01L23/5226 , H01L21/76829 , H01L23/53295
摘要： Methods of forming semiconductor devices including an air gap extending through at least one metal layer, and the semiconductor device so formed, are disclosed. The air gap has a lower portion that contacts a silicide layer over a gate body of a transistor gate and has an inverted T-shape over the gate body. The air gap reduces the capacitance between a transistor gate in a device layer and adjacent wires and vias used to contact the source and drain of the transistor.
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69.发明公开公开(公告)号：US20230402317A1
公开(公告)日：2023-12-14
申请号：US17806131
申请日：2022-06-09
发明人： Curtis Chun-I Hsieh , Wei-Hui Hsu , Wanbing Yi , Juan Boon Tan
IPC分类号： H01L21/764 , H01L21/768
CPC分类号： H01L21/764 , H01L21/7682
摘要： A structure includes a first air gap including a first opening defined in a first dielectric layer and a second dielectric layer over the first opening and closing an end portion of the first opening. A second air gap may be over at least a portion of the first air gap. The second air gap includes a second opening defined in the second dielectric layer and a third dielectric layer over the second opening and closing an end portion of the second opening. The second air gap has a pointed lower end portion. In another version, the structure includes a first air gap in a first dielectric layer, a second dielectric layer over the first air gap, and a discrete dielectric member positioned in the second dielectric layer and aligned over the first air gap.
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公开(公告)号：US20230361173A1
公开(公告)日：2023-11-09
申请号：US18354941
申请日：2023-07-19
发明人： Bong Woong Mun , Wanbing Yi , Juan Boon Tan , Jeoung Mo Koo
IPC分类号： H01L29/06 , H01L21/762 , H01L23/528 , H01L23/14
CPC分类号： H01L29/0649 , H01L21/76224 , H01L23/528 , H01L23/147
摘要： A structure includes a galvanic isolation including a horizontal portion including a first redistribution layer (RDL) electrode in a first insulator layer, and a second RDL electrode in the first insulator layer laterally spaced from the first RDL electrode. An isolation break includes a trench defined in the first insulator layer between the first RDL electrode and the second RDL electrode, and at least one second insulator layer in the trench. The first insulator layer and the second insulator layer(s) are between the first RDL electrode and the second RDL electrode. The isolation may separate, for example, voltage domains having different voltage levels. A related method is also disclosed. The isolation may also include a vertical portion using the first RDL electrode and another electrode in a metal layer separated from the first RDL electrode by a plurality of interconnect dielectric layers.
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