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    Heterojunction bipolar transistor with reduced sub-collector length, method of manufacture and design structure
    61.
    发明授权
    Heterojunction bipolar transistor with reduced sub-collector length, method of manufacture and design structure 有权
    具有减小的集电极长度的异质结双极晶体管，制造方法和设计结构

    公开(公告)号：US09059138B2

    公开(公告)日：2015-06-16

    申请号：US13358180

    申请日：2012-01-25

    申请人： Renata Camillo-Castillo ,  Zhong-Xiang He ,  Jeffrey B. Johnson ,  Qizhi Liu ,  Xuefeng Liu

    发明人： Renata Camillo-Castillo ,  Zhong-Xiang He ,  Jeffrey B. Johnson ,  Qizhi Liu ,  Xuefeng Liu

    IPC分类号： H01L29/737 ,  G06F17/50 ,  H01L21/331 ,  H01L29/417 ,  H01L29/66 ,  H01L29/10

    CPC分类号： H01L29/417 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/7371

    摘要： A heterojunction bipolar transistor (HBT) structure, method of manufacturing the same and design structure thereof are provided. The HBT structure includes a semiconductor substrate having a sub-collector region therein. The HBT structure further includes a collector region overlying a portion of the sub-collector region. The HBT structure further includes an intrinsic base layer overlying at least a portion of the collector region. The HBT structure further includes an extrinsic base layer adjacent to and electrically connected to the intrinsic base layer. The HBT structure further includes an isolation region extending vertically between the extrinsic base layer and the sub-collector region. The HBT structure further includes an emitter overlying a portion of the intrinsic base layer. The HBT structure further includes a collector contact electrically connected to the sub-collector region. The collector contact advantageously extends through at least a portion of the extrinsic base layer.

    摘要翻译： 提供异质结双极晶体管（HBT）结构，其制造方法及其设计结构。 HBT结构包括其中具有亚集电极区域的半导体衬底。 HBT结构还包括覆盖子集电极区域的一部分的集电极区域。 HBT结构还包括覆盖集电极区域的至少一部分的本征基极层。 HBT结构还包括与本征基极层相邻并电连接的外部基极层。 HBT结构还包括在外部基极层和副集电极区之间垂直延伸的隔离区。 HBT结构还包括覆盖本征基极层的一部分的发射极。 HBT结构还包括电连接到子集电极区的集电极触点。 收集器触点有利地延伸穿过外部基极层的至少一部分。

    FABRICATING POLYSILICON MOS DEVICES AND PASSIVE ESD DEVICES
    62.
    发明申请
    FABRICATING POLYSILICON MOS DEVICES AND PASSIVE ESD DEVICES 有权
    制造POLYSILICON MOS器件和被动ESD器件

    公开(公告)号：US20140183753A1

    公开(公告)日：2014-07-03

    申请号：US13733243

    申请日：2013-01-03

    申请人： John J. Ellis-Monaghan ,  Michael J. Hauser ,  Zhong-Xiang He ,  Junjun Li ,  Xuefeng Liu ,  Anthony K. Stamper

    发明人： John J. Ellis-Monaghan ,  Michael J. Hauser ,  Zhong-Xiang He ,  Junjun Li ,  Xuefeng Liu ,  Anthony K. Stamper

    IPC分类号： H01L27/04 ,  H01L21/36

    CPC分类号： B81C1/00301 ,  B81B7/007 ,  B81B2207/094 ,  B81C1/00246 ,  B81C2203/0714 ,  B81C2203/0742 ,  H01L21/84 ,  H01L27/1203

    摘要： A semiconductor fabrication is described, wherein a MOS device and a MEMS device is fabricated simultaneously in the BEOL process. A silicon layer is deposited and etched to form a silicon film for a MOS device and a lower silicon sacrificial film for a MEMS device. A conductive layer is deposited atop the silicon layer and etched to form a metal gate and a first upper electrode. A dielectric layer is deposited atop the conductive layer and vias are formed in the dielectric layer. Another conductive layer is deposited atop the dielectric layer and etched to form a second upper electrode and three metal electrodes for the MOS device. Another silicon layer is deposited atop the other conductive layer and etched to form an upper silicon sacrificial film for the MEMS device. The upper and lower silicon sacrificial films are then removed via venting holes.

    摘要翻译： 描述了半导体制造，其中在BEOL工艺中同时制造MOS器件和MEMS器件。 沉积并蚀刻硅层以形成用于MOS器件的硅膜和用于MEMS器件的下硅牺牲膜。 导电层沉积在硅层顶部并被蚀刻以形成金属栅极和第一上电极。 介电层沉积在导电层顶上，并且通孔形成在电介质层中。 另一个导电层沉积在电介质层顶上并被蚀刻以形成用于MOS器件的第二上电极和三个金属电极。 另一硅层沉积在另一导电层的顶上，并被蚀刻以形成用于MEMS器件的上硅牺牲膜。 然后通过排气孔去除上部和下部硅牺牲膜。

    HETEROJUNCTION BIPOLAR TRANSISTOR WITH REDUCED SUB-COLLECTOR LENGTH, METHOD OF MANUFACTURE AND DESIGN STRUCTURE
    63.
    发明申请
    HETEROJUNCTION BIPOLAR TRANSISTOR WITH REDUCED SUB-COLLECTOR LENGTH, METHOD OF MANUFACTURE AND DESIGN STRUCTURE 有权
    具有减少集电极长度的异相双极晶体管，制造方法和设计结构

    公开(公告)号：US20130187198A1

    公开(公告)日：2013-07-25

    申请号：US13358180

    申请日：2012-01-25

    申请人： Renata Camillo-Castillo ,  Zhong-Xiang He ,  Jeffrey B. Johnson ,  Qizhi Liu ,  Xuefeng Liu

    发明人： Renata Camillo-Castillo ,  Zhong-Xiang He ,  Jeffrey B. Johnson ,  Qizhi Liu ,  Xuefeng Liu

    IPC分类号： H01L29/737 ,  G06F17/50 ,  H01L21/331

    CPC分类号： H01L29/417 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/7371

    摘要： A heterojunction bipolar transistor (HBT) structure, method of manufacturing the same and design structure thereof are provided. The HBT structure includes a semiconductor substrate having a sub-collector region therein. The HBT structure further includes a collector region overlying a portion of the sub-collector region. The HBT structure further includes an intrinsic base layer overlying at least a portion of the collector region. The HBT structure further includes an extrinsic base layer adjacent to and electrically connected to the intrinsic base layer. The HBT structure further includes an isolation region extending vertically between the extrinsic base layer and the sub-collector region. The HBT structure further includes an emitter overlying a portion of the intrinsic base layer. The HBT structure further includes a collector contact electrically connected to the sub-collector region. The collector contact advantageously extends through at least a portion of the extrinsic base layer.

    摘要翻译： 提供异质结双极晶体管（HBT）结构，其制造方法及其设计结构。 HBT结构包括其中具有亚集电极区域的半导体衬底。 HBT结构还包括覆盖子集电极区域的一部分的集电极区域。 HBT结构还包括覆盖集电极区域的至少一部分的本征基极层。 HBT结构还包括与本征基极层相邻并电连接的外部基极层。 HBT结构还包括在外部基极层和副集电极区之间垂直延伸的隔离区。 HBT结构还包括覆盖本征基极层的一部分的发射极。 HBT结构还包括电连接到子集电极区的集电极触点。 收集器触点有利地延伸穿过外部基极层的至少一部分。

    Interconnect structures and design structures for a radiofrequency integrated circuit
    66.
    发明授权
    Interconnect structures and design structures for a radiofrequency integrated circuit 有权
    射频集成电路的互连结构和设计结构

    公开(公告)号：US08791545B2

    公开(公告)日：2014-07-29

    申请号：US13560446

    申请日：2012-07-27

    申请人： Timothy J. Dalton ,  Ebenezer E. Eshun ,  Sarah L. Grunow ,  Zhong-Xiang He ,  Anthony K. Stamper

    发明人： Timothy J. Dalton ,  Ebenezer E. Eshun ,  Sarah L. Grunow ,  Zhong-Xiang He ,  Anthony K. Stamper

    IPC分类号： H01L21/02

    CPC分类号： H01L21/76885 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/76834 ,  H01L27/016 ,  H01L28/20 ,  H01L28/40

    摘要： Interconnect structures that include a passive element, such as a thin film resistor or a metal-insulator-metal (MIM) capacitor, methods for fabricating an interconnect structure that includes a passive element, and design structures embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, such as a radiofrequency integrated circuit. A top surface of a dielectric layer is recessed relative to a top surface of a conductive feature in the dielectric layer. The passive element is formed on the recessed top surface of the dielectric layer and includes a layer of a conductive material that is coplanar with, or below, the top surface of the conductive feature.

    摘要翻译： 包括诸如薄膜电阻器或金属 - 绝缘体 - 金属（MIM）电容器的无源元件的互连结构，用于制造包括无源元件的互连结构的方法，以及体现在机器可读介质中的设计结构，用于设计， 制造或测试诸如射频集成电路的集成电路。 电介质层的顶表面相对于电介质层中导电特征的顶表面凹陷。 无源元件形成在介电层的凹入的顶表面上，并且包括与导电特征的顶表面共面或低于导电特征的顶表面的导电材料层。

    SEMICONDUCTOR SWITCHING DEVICE EMPLOYING A QUANTUM DOT STRUCTURE
    69.
    发明申请
    SEMICONDUCTOR SWITCHING DEVICE EMPLOYING A QUANTUM DOT STRUCTURE 有权
    半导体开关器件采用量子点结构

    公开(公告)号：US20120261745A1

    公开(公告)日：2012-10-18

    申请号：US13534462

    申请日：2012-06-27

    申请人： Zhong-Xiang He ,  Qizhi Liu

    发明人： Zhong-Xiang He ,  Qizhi Liu

    IPC分类号： H01L29/78 ,  G06F17/50

    CPC分类号： H01L29/127 ,  B82Y10/00 ,  H01L29/0895 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/7606 ,  H01L29/78

    摘要： A semiconductor device includes a semiconductor island having at least one electrical dopant atom and encapsulated by dielectric materials including at least one dielectric material layer. At least two portions of the at least one dielectric material layer have a thickness less than 2 nm to enable quantum tunneling effects. A source-side conductive material portion and a drain-side conductive material portion abuts the two portions of the at least one dielectric material layer. A gate conductor is located on the at least one dielectric material layer between the source-side conductive material portion and the drain-side conductive material portion. The potential of the semiconductor island responds to the voltage at the gate conductor to enable or disable tunneling current through the two portions of the at least one dielectric material layer. Design structures for the semiconductor device are also provided.

    摘要翻译： 半导体器件包括具有至少一个电掺杂剂原子并由包括至少一个电介质材料层的电介质材料包封的半导体岛。 所述至少一个电介质材料层的至少两部分具有小于2nm的厚度以实现量子隧道效应。 源极侧导电材料部分和漏极侧导电材料部分邻接至少一个介电材料层的两个部分。 栅极导体位于源极侧导电材料部分和漏极侧导电材料部分之间的至少一个介电材料层上。 半导体岛的电位响应栅极导体处的电压，以使得能够或不使穿过至少一个电介质材料层的两个部分的隧穿电流。 还提供了用于半导体器件的设计结构。

    METHOD OF ELECTROLYTIC PLATING AND SEMICONDUCTOR DEVICE FABRICATION
    70.
    发明申请
    METHOD OF ELECTROLYTIC PLATING AND SEMICONDUCTOR DEVICE FABRICATION 有权
    电解镀层和半导体器件制造方法

    公开(公告)号：US20120070979A1

    公开(公告)日：2012-03-22

    申请号：US12887737

    申请日：2010-09-22

    申请人： Felix P. Anderson ,  Zhong-Xiang He ,  Anthony K. Stamper ,  Eric J. White

    发明人： Felix P. Anderson ,  Zhong-Xiang He ,  Anthony K. Stamper ,  Eric J. White

    IPC分类号： H01L21/768 ,  C25D5/12 ,  C25D5/14 ,  H01L21/02

    CPC分类号： H01L21/7684 ,  C25D3/38 ,  C25D5/10 ,  C25D5/12 ,  H01L21/2885 ,  H01L21/76877

    摘要： The disclosure relates generally to semiconductor device fabrication, and more particularly to methods of electroplating used in semiconductor device fabrication. A method of electroplating includes: immersing an in-process substrate into an electrolytic plating solution to form a first metal layer on the in-process substrate; then performing a first chemical-mechanical polish to a liner on the in-process substrate followed by immersing the in-process substrate into the electrolytic plating solution to form a second metal layer on the first metal layer and the liner; and performing a second chemical-mechanical polish to the liner.

    摘要翻译： 本公开一般涉及半导体器件制造，更具体地涉及用于半导体器件制造中的电镀方法。 电镀方法包括：将处理后的基板浸入电解镀液中以在工艺衬底上形成第一金属层; 然后对所述工艺衬底上的衬垫进行第一化学机械抛光，然后将所述工艺衬底浸入所述电解电镀溶液中，以在所述第一金属层和所述衬垫上形成第二金属层; 以及对所述衬垫执行第二化学机械抛光。