公开(公告)号：US20150333023A1

公开(公告)日：2015-11-19

申请号：US14715778

申请日：2015-05-19

Applicant: Infineon Technologies AG

Inventor： Gottfried Beer ,  Raimund Foerg ,  Juergen Hoegerl

IPC: H01L23/00

CPC classification number: H01L24/14 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/03614 ,  H01L2224/0381 ,  H01L2224/039 ,  H01L2224/03912 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05552 ,  H01L2224/05555 ,  H01L2224/05562 ,  H01L2224/05564 ,  H01L2224/05582 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06131 ,  H01L2224/06132 ,  H01L2224/06133 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/06177 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11825 ,  H01L2224/119 ,  H01L2224/13012 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13562 ,  H01L2224/13644 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14131 ,  H01L2224/14132 ,  H01L2224/14133 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/14177 ,  H01L2224/16145 ,  H01L2224/26145 ,  H01L2224/32145 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06568 ,  H01L2924/13055 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/01015 ,  H01L2924/01074 ,  H01L2924/00012 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2224/03464

Abstract: A semiconductor device includes a semiconductor chip and a plurality of electrical contact pads disposed on a main face of the semiconductor chip, wherein the electrical contact pads each include a layer stack, each layer stack having one and the same order of layers, and wherein the electrical contact pads are both solderable and bondable.

Abstract translation: 半导体器件包括半导体芯片和设置在半导体芯片的主面上的多个电接触焊盘，其中电接触焊盘各自包括层堆叠，每个层堆叠具有一层且相同的层数，并且其中 电接触焊盘都是可焊接和可焊接的。

公开(公告)号：US09064869B2

公开(公告)日：2015-06-23

申请号：US13974583

申请日：2013-08-23

Applicant: Infineon Technologies AG

Inventor： Juergen Hoegerl ,  Edward Fuergut ,  Gottfried Beer ,  Olaf Hohlfeld

IPC: H01L23/18 ,  H01L21/60 ,  H01L23/522 ,  H01L23/00 ,  H01L23/28 ,  H01L23/31 ,  H01L23/485 ,  H01L25/18 ,  H01L27/12

CPC classification number: H01L23/5226 ,  H01L21/561 ,  H01L21/568 ,  H01L23/28 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3735 ,  H01L23/485 ,  H01L23/49811 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/09 ,  H01L24/24 ,  H01L24/29 ,  H01L24/73 ,  H01L24/82 ,  H01L24/83 ,  H01L24/89 ,  H01L24/92 ,  H01L25/18 ,  H01L27/12 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/2413 ,  H01L2224/24137 ,  H01L2224/291 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/92244 ,  H01L2924/1203 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/014

Abstract: The semiconductor module includes a carrier, a plurality of semiconductor transistor chips disposed on the carrier, a plurality of semiconductor diode chips disposed on the carrier, an encapsulation layer disposed above the semiconductor transistor chips and the semiconductor diode chips, and a metallization layer disposed above the encapsulation layer. The metallization layer includes a plurality of metallic areas forming electrical connections between selected ones of the semiconductor transistor chips and the semiconductor diode chips.

Abstract translation: 半导体模块包括载体，设置在载体上的多个半导体晶体管芯片，设置在载体上的多个半导体二极管芯片，设置在半导体晶体管芯片和半导体二极管芯片上方的封装层以及设置在半导体二极管芯片上方的金属化层 封装层。 金属化层包括形成半导体晶体管芯片中选定的半导体晶体管芯片和半导体二极管芯片之间的电连接的多个金属区域。

公开(公告)号：US20150076636A1

公开(公告)日：2015-03-19

申请号：US14027710

申请日：2013-09-16

Applicant: Infineon Technologies AG

Inventor： Gottfried Beer ,  Volker Strutz ,  Horst Theuss

IPC: H01L29/82 ,  G01R33/00 ,  H01L23/528 ,  G01R19/00 ,  H01L21/56 ,  H01L23/29

CPC classification number: H01L29/82 ,  G01R15/207 ,  G01R19/0092 ,  G01R33/0047 ,  G01R33/0052 ,  H01L21/561 ,  H01L21/568 ,  H01L23/293 ,  H01L23/3121 ,  H01L23/528 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2924/19105

Abstract: A current sensor device for sensing a measuring current includes a semiconductor chip having a magnetic field sensitive element. The current sensor device further includes an encapsulant embedding the semiconductor chip. A conductor configured to carry the measuring current is electrically insulated from the magnetic field sensitive element. A redistribution structure includes a first metal layer having a first structured portion which forms part of the conductor.

Abstract translation: 用于感测测量电流的电流传感器装置包括具有磁场敏感元件的半导体芯片。 电流传感器装置还包括嵌入半导体芯片的密封剂。 构造成承载测量电流的导体与磁场敏感元件电绝缘。 再分布结构包括具有形成导体的一部分的第一结构化部分的第一金属层。

公开(公告)号：US20150054166A1

公开(公告)日：2015-02-26

申请号：US14462693

申请日：2014-08-19

Applicant: Infineon Technologies AG

Inventor： Gottfried Beer ,  Edward Fuergut ,  Juergen Hoegerl ,  Olaf Hohlfeld ,  Peter Kanschat

IPC: H01L23/31 ,  H01L21/66 ,  H01L21/56 ,  H01L21/78 ,  H01L27/02 ,  H01L23/522

CPC classification number: H01L21/78 ,  H01L21/4875 ,  H01L21/56 ,  H01L21/563 ,  H01L21/565 ,  H01L22/10 ,  H01L22/14 ,  H01L23/051 ,  H01L23/31 ,  H01L23/522 ,  H01L24/96 ,  H01L25/072 ,  H01L25/115 ,  H01L27/02 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/2518 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A semiconductor arrangement includes a plurality of chip assemblies, each of which includes a semiconductor chip having a semiconductor body with a top side and an underside, a top main electrode arranged on the top side, a bottom main electrode arranged on the underside, an electrically conductive top compensation lamina arranged on a side of the top main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the top main electrode, an electrically conductive bottom compensation lamina arranged on a side of the bottom main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the bottom main electrode, and a dielectric embedding compound enclosing the semiconductor chip laterally circumferentially in a ring-shaped fashion such that the side of the compensation laminae facing away from the semiconductor body are at least not completely covered by the embedding compound.

Abstract translation: 半导体装置包括多个芯片组件，每个芯片组件包括半导体芯片，半导体芯片具有顶侧和下侧的半导体主体，布置在顶侧的顶部主电极，布置在下侧的底部主电极，电气 导电顶部补偿层布置在顶部主电极的背离半导体主体的一侧并且内导电地连接到顶部主电极，导电底部补偿层布置在底部主电极的背离 半导体本体并且内导电地连接到底部主电极，以及环形化方式围绕半导体芯片横向周向的电介质嵌入化合物，使得补偿层的背离半导体本体的一侧至少不是完全的 被包埋化合物覆盖。

公开(公告)号：US08759207B2

公开(公告)日：2014-06-24

申请号：US13671583

申请日：2012-11-08

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim Barth ,  Mathias Vaupel ,  Rainer Steiner ,  Werner Robl ,  Jens Pohl ,  Joem Plagmann ,  Gottfried Beer

IPC: H01L21/20

CPC classification number: H01L21/76843 ,  H01L21/76807 ,  H01L21/76879 ,  H01L23/49816 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L24/03 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/0106 ,  H01L2924/01068 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/00

Abstract: One or more embodiments relate to a method of forming a semiconductor structure, comprising: providing a workpiece; forming a barrier layer over the workpiece; forming a seed layer over the barrier layer; forming an inhibitor layer over the seed layer; removing a portion of said inhibitor layer to expose a portion of the seed layer; and selectively depositing a fill layer on the exposed seed layer.

Abstract translation: 一个或多个实施例涉及一种形成半导体结构的方法，包括：提供工件; 在工件上形成阻挡层; 在阻挡层上形成种子层; 在种子层上形成抑制层; 去除所述抑制剂层的一部分以暴露所述种子层的一部分; 并且在曝光的种子层上选择性地沉积填充层。