公开(公告)号：US09450180B1

公开(公告)日：2016-09-20

申请号：US14968287

申请日：2015-12-14

Applicant: International Business Machines Corporation

Inventor： Anthony J. Annunziata ,  Gen P. Lauer ,  Nathan P. Marchack

IPC: H01L43/12 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

CPC classification number: H01L43/08 ,  G11C11/161 ,  H01L27/222 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

Abstract: A method of making a magnetic random access memory (MRAM) device includes depositing a spacer material on an electrode; forming a magnetic tunnel junction (MTJ) on the spacer material that includes a reference layer in contact with the spacer material, a free layer, and a tunnel barrier layer; patterning a hard mask on the free layer; etching the MTJ and the spacer material to transfer a pattern of the hard mask into the MTJ and the spacer material; forming an insulating layer along a sidewall of the hard mask, the MTJ, and the spacer material; disposing an interlayer dielectric (ILD) on and around the hard mask, MTJ, and spacer material; etching through the ILD to form a trench that extends to a surface and sidewall of the hard mask and a sidewall of a portion of the MTJ; and disposing a metal in the trench to form a contact electrode.

Abstract translation: 制造磁性随机存取存储器（MRAM）器件的方法包括在电极上沉积间隔物材料; 在所述间隔材料上形成磁性隧道结（MTJ），所述磁性隧道结（MTJ）包括与所述间隔物材料接触的参考层，自由层和隧道势垒层; 在自由层上图案化硬掩模; 蚀刻MTJ和间隔物材料以将硬掩模的图案转移到MTJ和间隔物材料中; 沿着硬掩模，MTJ和间隔物材料的侧壁形成绝缘层; 在硬掩模，MTJ和间隔物材料上和周围设置层间电介质（ILD）; 通过ILD蚀刻以形成延伸到硬掩模的表面和侧壁以及MTJ的一部分的侧壁的沟槽; 并在沟槽中设置金属以形成接触电极。

公开(公告)号：US09397287B1

公开(公告)日：2016-07-19

申请号：US14982967

申请日：2015-12-29

Applicant: International Business Machines Corporation

Inventor： Anthony J. Annunziata ,  Chandrasekharan Kothandaraman ,  Gen P. Lauer

IPC: H01L43/08 ,  H01L43/02 ,  G11C11/16 ,  H01L43/12

CPC classification number: H01L43/08 ,  G11C11/161 ,  H01L43/02 ,  H01L43/12

Abstract: According to an embodiment of the invention, a method of making a magnetic random access memory device includes: forming a magnetic tunnel junction on an electrode, the magnetic tunnel junction comprising a reference layer positioned in contact with the electrode, a tunnel barrier layer arranged on the reference layer, and a free layer arranged on the tunnel barrier layer; depositing an encapsulating layer on and along sidewalls of the magnetic tunnel junction; depositing an interlayer dielectric layer on the encapsulating layer disposed on the magnetic tunnel junction; annealing the magnetic tunnel junction; and implanting hydrogen in a portion of the magnetic tunnel junction. According to another embodiment of the invention, implanting of hydrogen in a portion of the magnetic tunnel junction occurs after forming a magnetic tunnel junction trench. An MRAM device with hydrogen atoms incorporated in a portion of the magnetic tunnel junction is also disclosed.

Abstract translation: 根据本发明的实施例，一种制造磁性随机存取存储器件的方法包括：在电极上形成磁性隧道结，所述磁性隧道结包括与所述电极接触定位的参考层，所述隧道势垒层布置在 参考层和布置在隧道势垒层上的自由层; 在所述磁性隧道结的侧壁上沉积封装层; 在设置在磁隧道结上的封装层上沉积层间介电层; 退火磁隧道结; 以及在所述磁性隧道结的一部分中注入氢。 根据本发明的另一实施例，在形成磁隧道结沟槽之后，在磁隧道结的一部分中注入氢。 还公开了在磁性隧道结的一部分中并入氢原子的MRAM器件。

公开(公告)号：US20160099338A1

公开(公告)日：2016-04-07

申请号：US14505849

申请日：2014-10-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Josephine B. Chang ,  Michael A. Guillorn ,  Gen P. Lauer ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC: H01L29/66 ,  H01L29/10 ,  H01L21/3213 ,  H01L29/06 ,  H01L21/02 ,  H01L21/321 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L29/1037 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/32115 ,  H01L21/32134 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/401 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78696 ,  H01L2029/7858

Abstract: A method of making a field-effect transistor device includes providing a substrate with a fin stack having: a first sacrificial material layer on the substrate, a first semiconductive material layer on the first sacrificial material layer, and a second sacrificial material layer on the first semiconductive material layer. The method includes inserting a dummy gate having a second thickness, a dummy void, and an outer end that is coplanar to the second face. The method includes inserting a first spacer having a first thickness and a first void, and having an outer end that is coplanar to the first face. The method includes etching the first sacrificial material layer in the second plane and the second sacrificial material layer in the fourth plane. The method includes removing, at least partially, the first spacer. The method also includes inserting a second spacer having the first thickness.

公开(公告)号：US20150287650A1

公开(公告)日：2015-10-08

申请号：US14245683

申请日：2014-04-04

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Gen P. Lauer ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC: H01L21/84 ,  H01L21/02 ,  H01L21/24 ,  H01L27/12 ,  H01L21/225 ,  H01L29/66 ,  H01L29/735 ,  H01L21/3065 ,  H01L21/324

CPC classification number: H01L21/845 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/0257 ,  H01L21/02595 ,  H01L21/225 ,  H01L21/2254 ,  H01L21/2255 ,  H01L21/244 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/10826 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/06 ,  H01L29/0673 ,  H01L29/1008 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/6625 ,  H01L29/6631 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/735 ,  H01L29/775 ,  H01L29/7831 ,  H01L29/785 ,  H01L29/78696

Abstract: In one aspect, a method of fabricating a bipolar transistor device on a wafer includes the following steps. Fin hardmasks are formed on the wafer. A dummy gate is formed on the wafer, over the fin hardmasks. The wafer is doped to form emitter and collector regions on both sides of the dummy gate. A dielectric filler layer is deposited onto the wafer and the dummy gate is removed selective to the dielectric filler layer so as to form a trench in the filler layer. Fins are patterned in the wafer using the fin hardmasks exposed within the trench, wherein the fins will serve as a base region of the bipolar transistor device. The fins are recessed in the base region. The base region is re-grown from an epitaxial SiGe, Ge or III-V semiconductor material. A contact is formed to the base region.

Abstract translation: 一方面，在晶片上制造双极晶体管器件的方法包括以下步骤。 翅片硬掩模形成在晶片上。 在晶片上，在翅片硬掩模上形成虚拟栅极。 晶圆被掺杂以在虚拟栅极的两侧上形成发射极和集电极区域。 将介电填料层沉积在晶片上，并且将虚拟栅极选择性地去除介电填料层，以便在填料层中形成沟槽。 使用暴露在沟槽内的散热片硬掩模，在晶片中图案化鳍片，其中鳍片将用作双极晶体管器件的基极区域。 翅片凹入基部区域。 从外延SiGe，Ge或III-V半导体材料再生长基极区。 在基部区域形成接触。

公开(公告)号：US20150021715A1

公开(公告)日：2015-01-22

申请号：US13947316

申请日：2013-07-22

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Michael A. Guillorn ,  Gen P. Lauer ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823431 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/845 ,  H01L29/0665 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/41775 ,  H01L29/66439 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785

Abstract: Techniques for integrating low temperature salicide formation in a replacement gate device process flow are provided. In one aspect, a method of fabricating a FET device is provided that includes the following steps. A dummy gate(s) is formed over an active area of a wafer. A gap filler material is deposited around the dummy gate. The dummy gate is removed selective to the gap filler material, forming a trench in the gap filler material. A replacement gate is formed in the trench in the gap filler material. The replacement gate is recessed below a surface of the gap filler material. A gate cap is formed in the recess above the replacement gate. The gap filler material is etched back to expose at least a portion of the source and drain regions of the device. A salicide is formed on source and drain regions of the device.

Abstract translation: 提供了在替代浇口装置工艺流程中集成低温自对准硅化物形成技术。 一方面，提供了一种制造FET器件的方法，包括以下步骤。 在晶片的有效区域上形成虚拟栅极。 间隙填充材料沉积在虚拟栅极周围。 虚拟栅极被选择性地移除到间隙填充材料上，在间隙填充材料中形成沟槽。 在间隙填充材料的沟槽中形成替换栅极。 更换浇口凹陷在间隙填充材料的表面下方。 在替换门上方的凹槽中形成栅极盖。 间隙填充材料被回蚀以暴露该器件的源极和漏极区域的至少一部分。 在设备的源极和漏极区域上形成自对准硅化物。

公开(公告)号：US20140322907A1

公开(公告)日：2014-10-30

申请号：US14328921

申请日：2014-07-11

Applicant: International Business Machines Corporation

Inventor： Matthew J. BrightSky ,  Chung H. Lam ,  Gen P. Lauer

IPC: H01L21/28 ,  H01L27/24

CPC classification number: H01L21/28008 ,  H01L27/2454 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144

Abstract: A method to prevent a gate contact from electrically connecting to a source contact for a plurality of memory cells on a substrate. The method includes depositing and etching gate material to partially fill a space between the pillars and to form a word line for the memory cells, etching a gate contact region for the word line between the pair of pillars, forming a spacer of electrically insulating material in the gate contact region, and depositing a gate contact between the pair of pillars to be in electrical contact with the gate material such that the spacer surrounds the gate contact.

Abstract translation: 一种防止栅极接触与衬底上的多个存储器单元的源极接触电连接的方法。 该方法包括沉积和蚀刻栅极材料以部分地填充柱之间的空间并形成用于存储单元的字线，蚀刻一对柱之间的字线的栅极接触区域，形成电绝缘材料的间隔物 所述栅极接触区域以及在所述一对柱之间沉积栅极接触以与所述栅极材料电接触，使得所述间隔物围绕所述栅极接触。