公开(公告)号：US20180277669A1

公开(公告)日：2018-09-27

申请号：US15464768

申请日：2017-03-21

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Xin Miao ,  Wenyu Xu ,  Chen Zhang

IPC: H01L29/76 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/7613 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78696

Abstract: A semiconductor device includes a single electron transistor (SET) having an island region, a bottom source/drain region under the island region, and a top source/drain region over the island region, a first gap between the bottom source/drain region and the island region, a second gap between the top source/drain region and the island region, and a gate structure on a side of the island region.

公开(公告)号：US10069015B2

公开(公告)日：2018-09-04

申请号：US15276372

申请日：2016-09-26

Applicant: International Business Machines Corporation ,  Globalfoundries Inc.

Inventor： Kangguo Cheng ,  Xin Miao ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L29/06 ,  H01L29/786 ,  H01L29/423 ,  H01L29/66

Abstract: In one aspect, a method of forming a semiconductor device includes the steps of: forming an alternating series of sacrificial/active layers on a wafer and patterning it into at least one nano device stack; forming a dummy gate on the nano device stack; patterning at least one upper active layer in the nano device stack to remove all but a portion of the at least one upper active layer beneath the dummy gate; forming spacers on opposite sides of the dummy gate covering the at least one upper active layer that has been patterned; forming source and drain regions on opposite sides of the nano device stack, wherein the at least one upper active layer is separated from the source and drain regions by the spacers; and replacing the dummy gate with a replacement gate. A masking process is also provided to tailor the effective device width of select devices.

公开(公告)号：US20180240716A1

公开(公告)日：2018-08-23

申请号：US15436013

申请日：2017-02-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Xin Miao ,  Wenyu Xu ,  Chen Zhang

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/04

CPC classification number: H01L21/823892 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/823885 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/045 ,  H01L29/7827

Abstract: A technique relates to forming a semiconductor device. A first substrate is provided adjacent to a second substrate. The first substrate has a first surface orientation, and the second substrate has a second surface orientation different from the first surface orientation. An n-type field effect transistor (NFET) device is formed with the first substrate. The NFET device includes a first source, a first drain, and one or more first fins. The first source and the first drain have a vertical relationship with respect to the one or more first fins. A p-type field effect transistor (PFET) device is formed with the second substrate. The PFET device includes a second source, a second drain, and one or more second fins. The second source and the second drain have a vertical relationship with respect to the one or more second fins.

公开(公告)号：US20180212024A1

公开(公告)日：2018-07-26

申请号：US15925051

申请日：2018-03-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GlobalFoundries Inc.

Inventor： Kangguo Cheng ,  Xin Miao ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L29/06 ,  H01L29/786 ,  H01L21/02 ,  H01L29/775 ,  H01L29/66 ,  H01L29/423 ,  H01L27/12 ,  H01L27/092 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/265

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02252 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/26566 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78606 ,  H01L29/78618 ,  H01L29/78654 ,  H01L29/78684 ,  H01L29/78696

Abstract: A method of making a nanowire device includes disposing a first nanowire stack over a substrate, the first nanowire stack including alternating layers of a first and second semiconducting material, the first semiconducting material contacting the substrate and the second semiconducting material being an exposed surface; disposing a second nanowire stack over the substrate, the second nanowire stack including alternating layers of the first and second semiconducting materials, the first semiconducting material contacting the substrate and the second semiconducting material being an exposed surface; forming a first gate spacer along a sidewall of a first gate region on the first nanowire stack and a second gate spacer along a sidewall of a second gate region on the second nanowire stack; oxidizing a portion of the first nanowire stack within the first gate spacer; and removing the first semiconducting material from the first nanowire stack and the second nanowire stack.

公开(公告)号：US10002809B2

公开(公告)日：2018-06-19

申请号：US15622614

申请日：2017-06-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Zuoguang Liu ,  Xin Miao ,  Wenyu Xu ,  Chen Zhang

IPC: H01L21/66 ,  H01L29/786 ,  H01L29/423 ,  H01L29/78 ,  G01R31/28 ,  G01R27/20 ,  H01L21/8234 ,  H01L27/06 ,  G01R31/26

CPC classification number: H01L22/32 ,  G01R27/205 ,  G01R31/2621 ,  G01R31/2813 ,  G01R31/2856 ,  H01L21/76838 ,  H01L21/823487 ,  H01L21/823821 ,  H01L21/823885 ,  H01L21/845 ,  H01L22/14 ,  H01L22/34 ,  H01L27/0629 ,  H01L29/42392 ,  H01L29/6609 ,  H01L29/66136 ,  H01L29/66204 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/66795 ,  H01L29/7788 ,  H01L29/7802 ,  H01L29/7827 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78696

Abstract: A test device includes a diode junction layer having a first dopant conductivity region and a second dopant conductivity region formed within the diode junction layer on opposite sides of a diode junction. A first portion of vertical transistors is formed over the first dopant conductivity region as a device under test, and a second portion of vertical transistors is formed over the second dopant conductivity region. A common source/drain region is formed over the first and second portions of vertical transistors. Current through the first portion of vertical transistors permits measurement of a resistance at a probe contact connected to the common source/drain region.

公开(公告)号：US09997618B2

公开(公告)日：2018-06-12

申请号：US15476164

申请日：2017-03-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Ramachandra Divakaruni ,  Juntao Li ,  Xin Miao

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/10 ,  H01L29/08

CPC classification number: H01L29/6681 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7853

Abstract: Transistors and methods of forming the same include forming a fin of alternating layers of a channel material and a sacrificial material. Stress liners are formed in contact with both ends of the fin. The stress liners exert a stress on the fin. The sacrificial material is etched away from the fin, such that the layers of the channel material are suspended between the stress liners. A gate stack is formed over and around the suspended layers of channel material.

公开(公告)号：US09985021B2

公开(公告)日：2018-05-29

申请号：US15498460

申请日：2017-04-26

Applicant: International Business Machines Corporation

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Bruce Miao ,  Xin Miao

IPC: H01L21/311 ,  H01L27/088 ,  H01L29/66 ,  H01L29/06 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/78 ,  H01L21/02 ,  H01L21/027

CPC classification number: H01L27/088 ,  H01L21/0217 ,  H01L21/0274 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/823481 ,  H01L21/823487 ,  H01L29/0649 ,  H01L29/66666 ,  H01L29/7827

Abstract: A semiconductor device includes structures formed in first and second regions of a semiconductor substrate. The structures in the first region are spaced with a pitch P. The first and second regions are separated by an isolation region with spacing S, wherein S is greater than P. A first insulating layer is deposited and recessed to a target depth in the first region, and to a second depth in the isolation region. The second depth is lower than the target depth. A first etch stop layer is formed over the recessed first insulating layer, and a second insulating layer is formed over the first etch stop layer to increase a level of insulating material in the isolation region to the same target depth in the first device region. The recessed first insulating layer, first etch stop layer, and second insulating layer form a uniform thickness shallow trench isolation layer.

公开(公告)号：US09972700B2

公开(公告)日：2018-05-15

申请号：US15617573

申请日：2017-06-08

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Xin Miao ,  Wenyu Xu ,  Chen Zhang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L21/3065 ,  H01L21/02 ,  H01L29/423

CPC classification number: H01L29/66666 ,  H01L21/02609 ,  H01L21/3065 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/41741 ,  H01L29/4238 ,  H01L29/42392 ,  H01L29/7827

Abstract: A vertical fin field-effect-transistor and a method for fabricating the same. The vertical fin field-effect-transistor includes a substrate, a first source/drain layer including a plurality of pillar structures, and a plurality of fins disposed on and in contact with the plurality of pillar structures. A doped layer epitaxially grown from the first source/drain layer is in contact with the plurality of fins and the plurality of pillar structures. A gate structure is disposed in contact with two or more fins in the plurality of fins. The gate structure includes a dielectric layer and a gate layer. A second source/drain layer is disposed on the gate structure. The method includes epitaxially growing a doped layer in contact with a plurality of fins and a plurality of pillar structures. A gate structure is formed in contact with two or more fins. A second source/drain layer is formed on the gate structure.

公开(公告)号：US09960164B2

公开(公告)日：2018-05-01

申请号：US15617472

申请日：2017-06-08

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Xin Miao ,  Wenyu Xu ,  Chen Zhang

IPC: H01L29/768 ,  H01L29/80 ,  H01L29/76 ,  H01L21/00 ,  H01L21/8238 ,  H01L21/336 ,  H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L23/535

CPC classification number: H01L27/0924 ,  H01L21/6835 ,  H01L21/76895 ,  H01L21/823821 ,  H01L21/823885 ,  H01L21/84 ,  H01L22/22 ,  H01L23/50 ,  H01L23/5286 ,  H01L23/535 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/7827 ,  H01L29/785 ,  H01L2221/68359

Abstract: Various embodiments disclose a method for fabricating vertical transistors. In one embodiment, a structure is formed comprising at least a first substrate, an insulator layer on the substrate, a first doped layer on the insulator layer, at least one fin structure in contact with the doped layer, a dielectric layer surrounding a portion of the fin structure, a gate layer on the dielectric layer, a second doped layer in contact with the fin structure, a first contact area in contact with the second doped layer, and at least a first interconnect in contact with the first contact area. The structure is flipped bonded to a second substrate. The first substrate and the insulator layer are removed to expose the first doped layer. A second contact area is formed in contact with the first doped layer. At least a second interconnect is formed in contact with the second contact area.

公开(公告)号：US20180102362A1

公开(公告)日：2018-04-12

申请号：US15612257

申请日：2017-06-02

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Xin Miao ,  Wenyu Xu ,  Chen Zhang

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/1083 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method of forming features of a finFET structure includes forming fins on a surface of a substrate. A first liner is formed around each fin and a shallow trench isolation region is formed around each fin. A dopant layer is implanted in each fin. A portion of the shallow trench isolation region is etched from each fin. A first portion of the structure is blocked and the first liner replaced with a second liner in a second portion of the structure.