公开(公告)号：US06727268B2

公开(公告)日：2004-04-27

申请号：US10461945

申请日：2003-06-13

申请人： Il Hwan Cho ,  Jee Woong Lim ,  Sang Wook Park ,  Hyung Chul Ryu ,  Ji Young Noh ,  Jong Hoon Kim ,  Myeong Yun Chae ,  Sung Hak Jung ,  Hyun Jung Park ,  Kyu Jeong Yeon ,  Kyoung Rae Kang

发明人： Il Hwan Cho ,  Jee Woong Lim ,  Sang Wook Park ,  Hyung Chul Ryu ,  Ji Young Noh ,  Jong Hoon Kim ,  Myeong Yun Chae ,  Sung Hak Jung ,  Hyun Jung Park ,  Kyu Jeong Yeon ,  Kyoung Rae Kang

IPC分类号： A61K31426

CPC分类号： C07D277/36 ,  A61K31/426

摘要： A 2-thioxothiazole derivative of formula 1 or a non-toxic salt thereof, a preparation method thereof, and a pharmaceutical composition containing the derivative or the salt as an active ingredient are provided: wherein: R represents hydrogen or methyl; X represents hydrogen, methyl, halogen, nitro, or methanesulfonyl.

摘要翻译： 提供式1的2-硫代噻唑衍生物或其无毒盐，其制备方法和含有该衍生物或盐作为活性成分的药物组合物：其中：R表示氢或甲基; X表示氢， 甲基，卤素，硝基或甲磺酰基。

公开(公告)号：US09850530B2

公开(公告)日：2017-12-26

申请号：US13881900

申请日：2011-10-27

申请人： Han Oh Park ,  Kwon Sic Kim ,  Yang Won Lee ,  Jin Il Lee ,  Byung Rae Jeong ,  Jong Hoon Kim

发明人： Han Oh Park ,  Kwon Sic Kim ,  Yang Won Lee ,  Jin Il Lee ,  Byung Rae Jeong ,  Jong Hoon Kim

IPC分类号： C12Q1/68 ,  B01L3/02 ,  C12Q1/02 ,  G01N35/02 ,  B01L7/00 ,  G01N35/00 ,  G01N35/04

CPC分类号： C12Q1/686 ,  B01L3/0227 ,  B01L3/0234 ,  B01L7/52 ,  B01L2300/0829 ,  B01L2300/1805 ,  B01L2400/0478 ,  B03C1/01 ,  B03C1/288 ,  B03C2201/26 ,  C12Q1/02 ,  C12Q1/6844 ,  G01N35/0098 ,  G01N35/028 ,  G01N2035/0425 ,  G01N2035/0465

摘要： The present invention relates to an automatic real-time quantitative amplification system which can perform analysis of various biological samples, and more particularly to an automatic real-time quantitative amplification system in which a plurality of decks for respectively accommodating biological samples are put in a deck storing/transferring device, whereby it is possible to automatically analyze an amount or existence of a target substance containing a target nucleic acid in the biologic sample, such as a particular gene, a particular, a particular pathogenic bacterium and a particular protein, by amplifying the target nucleic acid purified by some processes of purification, purification after culture, or purification after reaction of the target substance contained in the biological sample and then checking an amount of the amplified target nucleic acid.

公开(公告)号：US09159494B2

公开(公告)日：2015-10-13

申请号：US13191849

申请日：2011-07-27

申请人： Hyung Joon Kim ,  Jong Hoon Kim ,  Kang Heon Hur ,  Dae Bok Oh

发明人： Hyung Joon Kim ,  Jong Hoon Kim ,  Kang Heon Hur ,  Dae Bok Oh

IPC分类号： H01G7/00 ,  H01G4/30 ,  H01G4/12 ,  H01G4/008 ,  H01G4/012

CPC分类号： H01G4/30 ,  H01G4/0085 ,  H01G4/012 ,  H01G4/12 ,  H01G4/248 ,  Y10T29/43 ,  Y10T29/435

摘要： Disclosed are a multilayer ceramic condenser and a method of manufacturing the same. The method includes printing a plurality of stripe-type inner electrode patterns in parallel on ceramic green sheets; forming a laminate by staking the ceramic green sheets having the plurality of stripe-type inner electrode patterns printed thereon; cutting the laminate in order to have a structure in which first and second inner electrode patterns are alternately stacked; and forming a first side part and a second side part by applying ceramic slurry in order to cover the sides of the laminate to which the first and second inner electrode patterns are exposed.

摘要翻译： 公开了一种多层陶瓷电容器及其制造方法。 该方法包括在陶瓷生片上平行印刷多条条状内部电极图案; 通过在其上印刷多个条形内部电极图案的陶瓷生片进行铆接来形成层压体; 切割层压体以具有第一和第二内部电极图案交替堆叠的结构; 以及通过施加陶瓷浆料形成第一侧面部分和第二侧面部分，以覆盖第一和第二内部电极图案所暴露的层压体的侧面。

公开(公告)号：US09087333B2

公开(公告)日：2015-07-21

申请号：US13877612

申请日：2011-10-06

申请人： Byeong Sam Kim ,  Ji Young Kim ,  Jong Hoon Kim ,  Ouiwoung Kim ,  Ki Hyun Kwon ,  Yong Kon Park ,  Yoon Sook Kim ,  Junemo Koo

发明人： Byeong Sam Kim ,  Ji Young Kim ,  Jong Hoon Kim ,  Ouiwoung Kim ,  Ki Hyun Kwon ,  Yong Kon Park ,  Yoon Sook Kim ,  Junemo Koo

IPC分类号： C08C19/22 ,  G06Q30/00 ,  G06Q10/08 ,  G06K17/00

CPC分类号： G06Q30/00 ,  G06K2017/0077 ,  G06Q10/0832 ,  G06Q30/0283

摘要： Disclosed is a method of monitoring food quality including (a) receiving an environmental factor value sensed during transporting by a moving sensor tag attached to a container or palette on which a plurality of food is stacked, a time value sensing the environmental factor, and food information from a distribution company server; (b) receiving an environmental factor value sensed by a fixed sale sensor tag which matches the food information stored in the moving sensor tag, a time value sensing the environmental factor, and food information from the distribution company server; (c) measuring a current quality index for each individual quality analysis item and a total quality index based on the food information sensed by the moving sensor tag and the fixed sale sensor tag, the environmental factor values, and the time values sensing the environmental factors; (d) setting price of the food based on the measured quality index for each individual quality analysis item and total quality index; and (e) transmitting bar code information or electronic tag information (food information) corresponding to a plurality of food which matches inherent IDs of the fixed sale sensor tags, the quality index for each individual analysis item of the food, the total quality index, and the price of the food to the distribution company server.

摘要翻译： 本发明公开了一种监测食品质量的方法，其包括：（a）通过附着在其上堆叠有多个食物的容器或调色板上的移动传感器标签，感测环境因素的时间值和食物接收在运送期间感测到的环境因子值 来自分销公司服务器的信息; （b）接收由固定销售传感器标签检测到的环境因素值，该固定销售传感器标签与存储在移动传感器标签中的食物信息，感测环境因素的时间值和来自分发公司服务器的食物信息相匹配; （c）基于由移动传感器标签和固定销售传感器标签感测到的食物信息，环境因子值和感测环境因素的时间值来测量每个单独质量分析项目的当前质量指数和总质量指数 ; （d）根据每个品质分析项目的质量指标和总质量指标，确定食品的价格; 和（e）发送与多个食品相对应的条形码信息或电子标签信息（食品信息），该多个食品与固定销售传感器标签的固有ID匹配，食品的每个分析项目的质量指标，总质量指数， 并将食品的价格送到分销公司的服务器。

公开(公告)号：US08395245B2

公开(公告)日：2013-03-12

申请号：US11953967

申请日：2007-12-11

申请人： Jong Hoon Kim ,  Min Suk Suh ,  Seong Cheol Kim ,  Seung Taek Yang ,  Seung Hyun Lee

发明人： Jong Hoon Kim ,  Min Suk Suh ,  Seong Cheol Kim ,  Seung Taek Yang ,  Seung Hyun Lee

IPC分类号： H01L23/495

CPC分类号： H05K1/141 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2225/107 ,  H01L2225/1088 ,  H01L2225/1094 ,  H05K1/021 ,  H05K1/182 ,  H05K1/183 ,  H05K3/0061 ,  H05K2201/10371 ,  H05K2201/10545 ,  H05K2201/10674 ,  H05K2203/1572

摘要： A semiconductor package module includes a circuit board including a board body having a receiving portion and conductive patterns formed on the board body; a semiconductor package received in the receiving portion and having conductive terminals electrically connected to the conductive patterns and an s semiconductor chip electrically connected to the conductive terminals; and a connection member electrically connecting the conductive patterns and the conductive terminals. In the present invention, after a receiving portion having a receiving space is formed in the board body of a circuit board and a semiconductor package is received in the receiving portion, and a connection terminal of the semiconductor package and a conductive pattern of the board body are electrically connected using a connection member, a plurality of semiconductor packages can be stacked in a single circuit board without increasing the thickness thereby significantly improving data storage capacity and data processing speed of the semiconductor package module.

摘要翻译： 一种半导体封装模块，包括：电路板，包括具有接收部分的基板主体和形成在所述基板主体上的导电图案; 接收在所述接收部分中并且具有电连接到所述导电图案的导电端子和与所述导电端子电连接的半导体芯片的半导体封装; 以及电连接导电图案和导电端子的连接构件。 在本发明中，在电路基板的基板主体中形成具有接收空间的接收部分，并且在接收部分中接收半导体封装的接收部分，以及半导体封装的连接端子和板体的导电图案 使用连接构件电连接，多个半导体封装可以堆叠在单个电路板中而不增加厚度，从而显着提高半导体封装模块的数据存储容量和数据处理速度。

公开(公告)号：US08361838B2

公开(公告)日：2013-01-29

申请号：US13241812

申请日：2011-09-23

申请人： Seung Taek Yang ,  Min Suk Suh ,  Seung Hyun Lee ,  Jong Hoon Kim

发明人： Seung Taek Yang ,  Min Suk Suh ,  Seung Hyun Lee ,  Jong Hoon Kim

IPC分类号： H01L21/00 ,  H01L23/48

CPC分类号： H01L23/481 ,  H01L23/3128 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05548 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/05099

摘要： A stacked semiconductor package and a method for manufacturing the same are presented which exhibit a reduced electrical resistance and an increased junction force. The semiconductor package includes at least two semiconductor chips stacked upon each other. Each semiconductor chip has a plurality of bonding pads formed on upper surfaces and has via-holes. First wiring lines are located on the upper surfaces of the semiconductor chips, on the surfaces of the via-holes, and respectively connected onto their respective bonding pads. Second wiring lines are located on lower surfaces of the semiconductor chips and on the surfaces of the respective via-holes which connect to their respective first wiring lines. The semiconductor chips are stacked so that the first wiring lines on an upper surface of an upwardly positioned semiconductor chip are respectively joined with corresponding second wiring lines formed on a lower surface of a downwardly positioned semiconductor chip.

摘要翻译： 本发明提供一种叠层半导体封装及其制造方法，其具有降低的电阻和增加的接合力。 半导体封装包括彼此堆叠的至少两个半导体芯片。 每个半导体芯片具有形成在上表面上并具有通孔的多个接合焊盘。 第一布线位于半导体芯片的上表面上，位于通孔的表面上，分别连接到它们各自的接合焊盘上。 第二布线位于半导体芯片的下表面和连接到它们各自的第一布线的相应通孔的表面上。 半导体芯片被堆叠，使得位于向上定位的半导体芯片的上表面上的第一布线分别与形成在向下定位的半导体芯片的下表面上的相应的第二布线接合。

公开(公告)号：US20120147516A1

公开(公告)日：2012-06-14

申请号：US13191890

申请日：2011-07-27

申请人： Hyung Joon KIM ,  Jong Hoon Kim

发明人： Hyung Joon KIM ,  Jong Hoon Kim

IPC分类号： H01G4/30 ,  H01G4/12

CPC分类号： H01G4/1227 ,  H01G4/008 ,  H01G4/012 ,  H01G4/232 ,  H01G4/2325 ,  H01G4/30 ,  Y10T29/435

摘要： Disclosed are a multilayer ceramic condenser and a method for manufacturing the same. There is provided a multilayer ceramic condenser including: a multilayer main body in which a plurality of dielectric layers including a first side, a second side, a third side, and a fourth side are stacked; a first cover layer and a second cover layer forming the plurality of dielectric layers; a first dielectric layer disposed between the first cover layer and the second cover layer and printed with a first inner electrode pattern drawn to the first side; a second dielectric layer alternately stacked with the first dielectric layer and printed with a second inner electrode pattern drawn to the third side; and a first side portion and a second side portion each formed on the second side and the fourth side opposite to each other.

摘要翻译： 公开了一种多层陶瓷电容器及其制造方法。 提供了一种多层陶瓷电容器，包括：多层主体，其中堆叠包括第一侧，第二侧，第三侧和第四侧的多个电介质层; 形成所述多个电介质层的第一覆盖层和第二覆盖层; 第一电介质层，设置在第一覆盖层和第二覆盖层之间，并印刷有第一内部电极图案，其被绘制到第一侧; 第二电介质层，与所述第一电介质层交替堆叠并且印刷有第二内部电极图案，所述第二内部电极图案被绘制到所述第三侧; 以及分别形成在彼此相对的第二侧和第四侧上的第一侧部和第二侧部。

公开(公告)号：US08154135B2

公开(公告)日：2012-04-10

申请号：US12491651

申请日：2009-06-25

申请人： Jong Hoon Kim ,  Ho Young Son

发明人： Jong Hoon Kim ,  Ho Young Son

IPC分类号： H01L23/48 ,  H01L29/40

CPC分类号： H01L24/92 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/481 ,  H01L24/03 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05555 ,  H01L2224/0557 ,  H01L2224/056 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/06136 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/29 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/29298 ,  H01L2224/83194 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00013 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10158 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929

摘要： A stacked semiconductor package is presented which includes multiple semiconductor chips and through-electrodes. Each semiconductor chip has bonding pads formed on a first surface of the semiconductor chip and has a projection which projects from a portion of a second surface of the semiconductor chip. The first and second surfaces of the semiconductor chip face away from each other the first surface. The through-electrodes pass through the first surface and through the projection on the second surface.

摘要翻译： 提出了一种堆叠的半导体封装，其包括多个半导体芯片和通孔。 每个半导体芯片具有形成在半导体芯片的第一表面上的接合焊盘，并且具有从半导体芯片的第二表面的一部分突出的突起。 半导体芯片的第一和第二表面相对于第一表面。 贯通电极穿过第一表面并穿过第二表面上的突起。

公开(公告)号：US08110910B2

公开(公告)日：2012-02-07

申请号：US12731346

申请日：2010-03-25

申请人： Jong Hoon Kim

发明人： Jong Hoon Kim

IPC分类号： H01L23/02

CPC分类号： H01L21/568 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/24 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/0557 ,  H01L2224/1134 ,  H01L2224/12105 ,  H01L2224/13009 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/32188 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73257 ,  H01L2224/73259 ,  H01L2224/81005 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/05599

摘要： A stack package includes a first semiconductor chip possessing a first size and one or more second semiconductor chips possessing a second size greater than the first size. The first semiconductor chip has a first surface on which bonding pads are disposed, a second surface which faces away from the first surface, and first through-electrodes which pass through the first surface and the second surface. The one or more second semiconductor chips are stacked on the second surface of the first semiconductor chip and have second through-electrodes which are electrically connected to the first through-electrodes. A molding part abuts one or more side surfaces of the first semiconductor chip such that a total size including the first size and a size of the molding part is equal to or greater than the second size.

摘要翻译： 堆叠封装包括具有第一尺寸的第一半导体芯片和具有大于第一尺寸的第二尺寸的一个或多个第二半导体芯片。 第一半导体芯片具有设置接合焊盘的第一表面，远离第一表面的第二表面和穿过第一表面和第二表面的第一通孔。 一个或多个第二半导体芯片堆叠在第一半导体芯片的第二表面上，并且具有电连接到第一贯通电极的第二贯穿电极。 模制部件邻接第一半导体芯片的一个或多个侧表面，使得包括第一尺寸和成型部件的尺寸的总尺寸等于或大于第二尺寸。

公开(公告)号：US08018043B2

公开(公告)日：2011-09-13

申请号：US12261112

申请日：2008-10-30

申请人： Min Suk Suh ,  Seung Taek Yang ,  Seung Hyun Lee ,  Jong Hoon Kim

发明人： Min Suk Suh ,  Seung Taek Yang ,  Seung Hyun Lee ,  Jong Hoon Kim

IPC分类号： H01L23/48

CPC分类号： H01L23/4334 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/525 ,  H01L24/19 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/15311

摘要： A semiconductor package includes a semiconductor chip having an upper surface, side surfaces connected with the upper surface, and bonding pads formed on the upper surface. A first insulation layer pattern is formed to cover the upper surface and the side surfaces of the semiconductor chip and expose the bonding pads. Re-distribution lines are placed on the first insulation layer pattern and include first re-distribution line parts and second re-distribution line parts. The first re-distribution line parts have an end connected with the bonding pads and correspond to the upper surface of the semiconductor chip and the second re-distribution line parts extend from the first re-distribution line parts beyond the side surfaces of the semiconductor chip. A second insulation layer pattern is formed over the semiconductor chip and exposes portions of the first re-distribution line parts and the second re-distribution line parts.

摘要翻译： 半导体封装包括具有上表面的半导体芯片，与上表面连接的侧表面，以及形成在上表面上的焊盘。 形成第一绝缘层图案以覆盖半导体芯片的上表面和侧表面并且暴露接合焊盘。 再分配线路放置在第一绝缘层图案上，并且包括第一再分配线部分和第二再分配线部分。 第一再分配线部分具有与接合焊盘连接的端部并且对应于半导体芯片的上表面，并且第二再分配线部分从第一再分配线部分延伸超过半导体芯片的侧表面 。 在半导体芯片上形成第二绝缘层图案，并且暴露出第一再分配线部分和第二再分配线部分的部分。