公开(公告)号：US20060175627A1

公开(公告)日：2006-08-10

申请号：US11347290

申请日：2006-02-06

申请人： Masaki Shiraishi

发明人： Masaki Shiraishi

IPC分类号： H01L33/00 ,  H01L29/22

CPC分类号： H01L29/7787 ,  H01L23/49575 ,  H01L25/16 ,  H01L29/2003 ,  H01L29/7813 ,  H01L2224/0603 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/30107 ,  H01L2924/3011 ,  H02M3/1588 ,  Y02B70/1466 ,  Y02B70/1483 ,  H01L2924/00014 ,  H01L2924/00

摘要： A power supply includes a non-isolated DC-DC converter for use in a power source system having a high side switch and a low side switch, in which HEMT or HFET or gallium nitride device with low capacity and low on-resistance is used for the high side switch and a vertical power MOSFET of silicon device with low on-resistance is used for the low side switch.

摘要翻译： 电源包括用于具有高侧开关和低侧开关的电源系统中的非隔离DC-DC转换器，其中使用具有低容量和低导通电阻的HEMT或HFET或氮化镓器件用于 低侧开关使用高侧开关和具有低导通电阻的硅器件的垂直功率MOSFET。

公开(公告)号：US07066018B2

公开(公告)日：2006-06-27

申请号：US10832289

申请日：2004-04-27

申请人： Kazuyoshi Miyamoto ,  Masaki Shiraishi

发明人： Kazuyoshi Miyamoto ,  Masaki Shiraishi

IPC分类号： E01C23/00

CPC分类号： G06F17/5095 ,  B60C11/0318 ,  B60C19/00 ,  B60C99/006 ,  G01M17/02 ,  G06F17/5018

摘要： A method of simulating a tire rolling on a road includes modeling the tire in finite elements to make a tire model; modeling the surface of the road in finite elements to make a road model; executing a simulation in which the tire model is made to roll on the road model at a predetermined speed; and obtaining information about the tire model. The speed of the tire model is varied by repeating an increase and a decrease based on a predetermined reference speed.

摘要翻译： 模拟轮胎在道路上滚动的方法包括以有限元模拟轮胎以制造轮胎模型; 以有限元建模道路表面，形成道路模型; 执行轮胎模型以预定速度在道路模型上滚动的模拟; 并获取有关轮胎模型的信息。 通过基于预定的参考速度重复增加和减少来改变轮胎模型的速度。

公开(公告)号：US07019362B2

公开(公告)日：2006-03-28

申请号：US10781704

申请日：2004-02-20

申请人： Kozo Sakamoto ,  Takayuki Iwasaki ,  Masaki Shiraishi

发明人： Kozo Sakamoto ,  Takayuki Iwasaki ,  Masaki Shiraishi

IPC分类号： H01L29/76

CPC分类号： H01L24/02 ,  H01L29/0692 ,  H01L2224/0401 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13063 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00

摘要： The gate resistance of a power MOSFET in a semiconductor chip is reduced and the reliability and yield of the gate of the power MOSFET are improved The semiconductor chip includes two or more control electrode pads functioning as control electrodes for a power semiconductor device formed within a semiconductor chip. The two or more control electrode pads are distributed within the periphery of the gate area of the power semiconductor device such that the gate resistance of the power semiconductor device can be reduced. The two or more control electrode pads are connected via bumps or a conductive bonding material to an electrode layer of a multilayer circuit board disposed outside the semiconductor chip.

摘要翻译： 半导体芯片中的功率MOSFET的栅极电阻降低，并且功率MOSFET的栅极的可靠性和产量得到改善。半导体芯片包括用作形成在半导体内的功率半导体器件的控制电极的两个或更多个控制电极焊盘 芯片。 两个以上的控制电极焊盘分布在功率半导体器件的栅极区域的周围，使得能够降低功率半导体器件的栅极电阻。 两个以上的控制电极焊盘通过凸块或导电接合材料连接到设置在半导体芯片外部的多层电路板的电极层。

公开(公告)号：US20060006432A1

公开(公告)日：2006-01-12

申请号：US11175288

申请日：2005-07-07

申请人： Masaki Shiraishi ,  Takayuki Iwasaki ,  Nobuyoshi Matsuura

发明人： Masaki Shiraishi ,  Takayuki Iwasaki ,  Nobuyoshi Matsuura

IPC分类号： H01L29/76

CPC分类号： H01L29/7813 ,  H01L21/823487 ,  H01L24/48 ,  H01L24/49 ,  H01L25/16 ,  H01L27/088 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/4813 ,  H01L2224/48137 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/30107 ,  H02M3/1588 ,  Y02B70/1466 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A semiconductor device in which the self-turn-on phenomenon is prevented that can significantly improve power conversion efficiency. The semiconductor device is a system-in-package for power supply applications in which a high-side switch, a low-side switch, and two drivers are included in a single package. The device includes an auxiliary switch disposed between the gate and source of said low-side switch, and a low-side MOSFET 3 for the low-side switch and an auxiliary MOSFET 4 for the auxiliary switch are disposed on the same chip. In this way, the self-turn-on phenomenon can be prevented, allowing the mounting of a low-side MOSFET 3 with a low threshold voltage and thereby significantly improving power conversion efficiency. The gate of the auxiliary MOSFET 4 is driven by the driver for the high-side MOSFET 2, thereby eliminating the need for a new drive circuit and realizing the same pin configuration as existing products, which facilitates easy replacement.

摘要翻译： 能够防止能够显着提高电力转换效率的自启动现象的半导体装置。 半导体器件是用于电源应用的系统级封装，其中高侧开关，低侧开关和两个驱动器包括在单个封装中。 该装置包括设置在所述低侧开关的栅极和源极之间的辅助开关，并且用于低侧开关的低侧MOSFET 3和用于辅助开关的辅助MOSFET 4设置在同一芯片上。 以这种方式，可以防止自导通现象，允许安装具有低阈值电压的低端MOSFET 3，从而显着提高功率转换效率。 辅助MOSFET 4的栅极由用于高侧MOSFET 2的驱动器驱动，从而不需要新的驱动电路并实现与现有产品相同的引脚配置，这便于更换。

公开(公告)号：US20050029584A1

公开(公告)日：2005-02-10

申请号：US10886041

申请日：2004-07-08

申请人： Masaki Shiraishi ,  Yoshito Nakazawa

发明人： Masaki Shiraishi ,  Yoshito Nakazawa

IPC分类号： H01L29/78 ,  H01L21/265 ,  H01L21/336 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49

CPC分类号： H01L29/7811 ,  H01L21/26586 ,  H01L24/05 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813 ,  H01L2224/05552 ,  H01L2224/0603 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/00

摘要： A technology is provided to reduce ON-resistance, and the prevention of punch through is achieved with respect to a trench gate type power MISFET. Input capacitance and a feedback capacitance are reduced by forming a groove in which a gate electrode is formed so as to have a depth as shallow as about 1 μm or less, a p−type semiconductor region is formed to a depth so as not to cover the bottom of the groove, and a p-type semiconductor region higher in impurity concentration than the p−type semiconductor region is formed under a n+type semiconductor region serving as a source region of the trench gate type power MISFET, causing the p-type semiconductor region to serve as a punch-through stopper layer of the trench gate type power MISFET.

摘要翻译： 提供了一种降低导通电阻的技术，并且相对于沟槽栅型功率MISFET实现了穿通的防止。 输入电容和反馈电容通过形成栅极形成的沟槽而减小，使得其深度为1μm或更小的深度，形成深度不高于 覆盖凹槽的底部，并且在用作沟槽栅型功率MISFET的源极区域的+ +型半导体区域之下形成杂质浓度高于p型半导体区域的p型半导体区域， 导致p型半导体区域用作沟槽栅型功率MISFET的穿通阻挡层。

公开(公告)号：US06498368B2

公开(公告)日：2002-12-24

申请号：US09733098

申请日：2000-12-11

申请人： Kozo Sakamoto ,  Yosuke Inoue ,  Akihiro Miyauchi ,  Masaki Shiraishi ,  Mutsuhiro Mori ,  Atsuo Watanabe ,  Takasumi Ohyanagi

发明人： Kozo Sakamoto ,  Yosuke Inoue ,  Akihiro Miyauchi ,  Masaki Shiraishi ,  Mutsuhiro Mori ,  Atsuo Watanabe ,  Takasumi Ohyanagi

IPC分类号： H01L31119

CPC分类号： H01L29/7813 ,  H01L29/045 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/732 ,  H01L29/7397 ,  H01L29/7722 ,  H01L29/7811 ,  H01L29/872

摘要： In a semiconductor device having a first terminal 101 (source terminal) and a second terminal 102 (drain terminal), the substrate main surface of a semiconductor chip is on the (110) face, the main contact face of an n-type region 2 and a p-type region 4 is the {111} face perpendicular to the (110) face, elongated n-type regions 2 and elongated p-type regions 4, which are arranged alternately, form a voltage holding area. The first terminal 101 is connected to the p-type regions through wiring, and the second terminal 102 is connected to the n-type regions 2. Also, the p-type region is formed to cover the bottom comers of a gate polycrystalline silicon layer 8.

摘要翻译： 在具有第一端子101（源极端子）和第二端子102（漏极端子）的半导体器件中，半导体芯片的基板主表面在（110）面上，n型区域2的主接触面 并且p型区域4是垂直于（110）面的{111}面，交替布置的细长n型区域2和细长p型区域4形成电压保持区域。 第一端子101通过布线连接到p型区域，并且第二端子102连接到n型区域2.而且，形成p型区域以覆盖栅极多晶硅层的底部角 8。

公开(公告)号：US5309963A

公开(公告)日：1994-05-10

申请号：US594166

申请日：1990-10-09

申请人： Kiichiro Kakumu ,  Masaki Shiraishi ,  Hiroyuki Nakagawa ,  Hiroaki Sakuno ,  Yoshiichiro Iwahashi ,  Shigeaki Suzuki

发明人： Kiichiro Kakumu ,  Masaki Shiraishi ,  Hiroyuki Nakagawa ,  Hiroaki Sakuno ,  Yoshiichiro Iwahashi ,  Shigeaki Suzuki

IPC分类号： B60C11/04 ,  B60C11/00 ,  B60C11/03 ,  B60C11/11 ,  B60C11/13

CPC分类号： B60C11/0318 ,  B60C11/033 ,  B60C11/11 ,  Y10S152/902

摘要： A pneumatic tire has a tread pattern with blocks which are divided by two circumferential grooves extending in the circumferential direction of a tire and eighty-five or more lateral grooves crossing the circumferential grooves in a tread part. In the tread pattern, the quotient S.sub.T /S of the total groove area S.sub.T which is the sum of the circumferential groove area S.sub.G and the lateral groove area Sg in a ground contact surface S when the tire is mounted on a standard rim, inflated with a normal internal pressure and loaded with a normal load, to the ground contact area S is in a range from 0.15 to 0.25, and the rate Sg/S.sub.G of the lateral groove area Sg to the circumferential groove area S.sub.G is in a range from 0.33 to 0.53.

摘要翻译： 充气轮胎具有胎面花纹，胎面花纹具有沿轮胎周向延伸的两个周向槽和在胎面部分中与周向槽交叉的八十五个或更多个横向槽分隔的块。 在胎面花纹中，当轮胎安装在标准轮辋上时，总槽面积ST的商ST / S是周边槽区域SG和接地表面S中的横向槽区域Sg的总和，其膨胀 向接地区域S施加正常的内部压力并加载正常负载的正常内部压力在0.15至0.25的范围内，并且横向槽区域Sg与周向槽区域SG的速率Sg / SG在0.33 至0.53。

公开(公告)号：US08653588B2

公开(公告)日：2014-02-18

申请号：US13553431

申请日：2012-07-19

申请人： So Watanabe ,  Masaki Shiraishi ,  Hiroshi Suzuki ,  Mutsuhiro Mori

发明人： So Watanabe ,  Masaki Shiraishi ,  Hiroshi Suzuki ,  Mutsuhiro Mori

IPC分类号： H01L29/66

CPC分类号： H01L29/7397 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/66348

摘要： A semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type on the first semiconductor layer; trenches in the first semiconductor layer; a semiconductor protruding part on the first semiconductor layer; a third semiconductor layer on the semiconductor protruding part; a fourth semiconductor layer on the third semiconductor layer; a gate insulating layer disposed along the trench; a first interlayer insulating layer disposed along the trench; a first conductive layer facing to the fourth semiconductor layer; a second conductive layer on the first interlayer insulating layer; a second interlayer insulating layer covering the second conductive layer; a third conductive layer on the third semiconductor layer and fourth semiconductor layer; a contacting part connecting the third conductive layer and third semiconductor layer; and a fourth conductive layer formed on the second semiconductor layer.

摘要翻译： 半导体器件包括：第一导电类型的第一半导体层; 在第一半导体层上的第二导电类型的第二半导体层; 第一半导体层中的沟槽; 在所述第一半导体层上的半导体突出部; 半导体突出部分上的第三半导体层; 第三半导体层上的第四半导体层; 栅极绝缘层，沿着沟槽设置; 沿沟槽设置的第一层间绝缘层; 面向第四半导体层的第一导电层; 在第一层间绝缘层上的第二导电层; 覆盖所述第二导电层的第二层间绝缘层; 在第三半导体层和第四半导体层上的第三导电层; 连接第三导电层和第三半导体层的接触部分; 以及形成在所述第二半导体层上的第四导电层。

公开(公告)号：US08519533B2

公开(公告)日：2013-08-27

申请号：US13396073

申请日：2012-02-14

申请人： Masaki Shiraishi ,  Tomoaki Uno ,  Nobuyoshi Matsuura

发明人： Masaki Shiraishi ,  Tomoaki Uno ,  Nobuyoshi Matsuura

IPC分类号： H01L23/34

CPC分类号： H01L27/0629 ,  H01L21/28035 ,  H01L21/823475 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/06 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/4232 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/45 ,  H01L29/456 ,  H01L29/4916 ,  H01L29/66143 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/872 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/48624 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73221 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/20753 ,  H01L2924/20755 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H02M3/155 ,  H02M7/003

摘要： In a non-insulated DC-DC converter having a circuit in which a power MOS•FET high-side switch and a power MOS•FET low-side switch are connected in series, the power MOS•FET low-side switch and a Schottky barrier diode to be connected in parallel with the power MOS•FET low-side switch are formed within one semiconductor chip. The formation region SDR of the Schottky barrier diode is disposed in the center in the shorter direction of the semiconductor chip, and on both sides thereof, the formation regions of the power MOS•FET low-side switch are disposed. From the gate finger in the vicinity of both long sides on the main surface of the semiconductor chip toward the formation region SDR of the Schottky barrier diode, a plurality of gate fingers are disposed so as to interpose the formation region SDR between them.

摘要翻译： 在具有电源MOS.FET高侧开关和功率MOS.FET低侧开关串联连接的电路的非绝缘DC-DC转换器中，功率MOS.FET低侧开关和肖特基 与功率MOS.FET低侧开关并联连接的阻挡二极管形成在一个半导体芯片内。 肖特基势垒二极管的形成区域SDR设置在半导体芯片的较短方向的中心，并且在其两侧设置功率MOS.FET低侧开关的形成区域。 从半导体芯片的主表面的两长边附近的栅极指向肖特基势垒二极管的形成区域SDR，设置多个栅极指，以便在它们之间插入形成区域SDR。

公开(公告)号：US20120139130A1

公开(公告)日：2012-06-07

申请号：US13372227

申请日：2012-02-13

申请人： Yukihiro Satou ,  Tomoaki Uno ,  Nobuyoshi Matsuura ,  Masaki Shiraishi

发明人： Yukihiro Satou ,  Tomoaki Uno ,  Nobuyoshi Matsuura ,  Masaki Shiraishi

IPC分类号： H01L23/49

CPC分类号： H01L23/5386 ,  H01L23/49575 ,  H01L23/50 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L25/165 ,  H01L29/4175 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/29339 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/4943 ,  H01L2224/83855 ,  H01L2224/85 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/20753 ,  H01L2924/20755 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H02M3/1588 ,  H05K7/02 ,  Y02B70/1466 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/2075 ,  H01L2924/20754

摘要： The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS•FET for a high side switch and a power MOS•FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other.

摘要翻译： 本发明提供一种具有电路的非绝缘型DC-DC转换器，其中用于高侧开关的功率MOS•FET和低边开关的功率MOS•FET串联连接。 在非绝缘型DC-DC转换器中，用于高侧开关的功率晶体管，低边开关的功率晶体管和驱动它们的驱动电路分别由不同的半导体芯片构成。 三个半导体芯片被容纳在一个封装中，并且包括用于高侧开关的功率晶体管的半导体芯片和包括驱动电路的半导体芯片被布置成彼此接近。