公开(公告)号：US20100117051A1

公开(公告)日：2010-05-13

申请号：US12269507

申请日：2008-11-12

申请人： Wei Tian ,  Venkatram Venkatasamy ,  Ming Sun ,  Michael Xuefei Tang ,  Insik Jin ,  Dimitar V. Dimitrov

发明人： Wei Tian ,  Venkatram Venkatasamy ,  Ming Sun ,  Michael Xuefei Tang ,  Insik Jin ,  Dimitar V. Dimitrov

IPC分类号： H01L47/00 ,  H01L21/44

CPC分类号： H01L27/2472 ,  H01L21/76816 ,  H01L23/5226 ,  H01L27/228 ,  H01L27/2436 ,  H01L43/08 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1273 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/1625 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

摘要： A memory cell that includes a first contact having a first surface and an opposing second surface; a second contact having a first surface and an opposing second surface; a memory material layer having a first surface and an opposing second surface; and a nanoporous layer having a first surface and an opposing second surface, the nanoporous layer including at least one nanopore and dielectric material, the at least one nanopore being substantially filled with a conductive metal, wherein a surface of the nanoporous layer is in contact with a surface of the first contact or the second contact and the second surface of the nanoporous layer is in contact with a surface of the memory material layer.

摘要翻译： 一种存储单元，包括具有第一表面和相对的第二表面的第一触点; 具有第一表面和相对的第二表面的第二触点; 存储材料层，其具有第一表面和相对的第二表面; 以及具有第一表面和相对的第二表面的纳米多孔层，所述纳米多孔层包括至少一个纳米孔和介电材料，所述至少一个纳米孔基本上填充有导电金属，其中所述纳米多孔层的表面与 第一接触面或第二接触面的表面和纳米多孔层的第二表面与记忆材料层的表面接触。

公开(公告)号：US20100032819A1

公开(公告)日：2010-02-11

申请号：US12188160

申请日：2008-08-07

申请人： Kai Liu ,  Ming Sun

发明人： Kai Liu ,  Ming Sun

IPC分类号： H01L23/495 ,  H01L21/56

CPC分类号： H01L24/49 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/072 ,  H01L2224/37011 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/4103 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/37099

摘要： A semiconductor package is disclosed for packaging two adjacent semiconductor dies atop a circuit substrate. The dies are separated from each other along their longitudinal edges with an inter-die distance. An elevation-adaptive electrical connection connects a top metalized contact of die two to the bottom surface of die one while accommodating for elevation difference between the surfaces. The elevation-adaptive electrical connection includes: a) An L-shaped circuit route that is part of the circuit substrate, extending transversely from a die one longitudinal edge and placing an intermediate contact area next to a die two transverse edge. b) An interconnection plate connecting the top metalized contact area of die two with the intermediate contact area while being formed to accommodate for elevation difference between the contact areas. Consequently, the semiconductor package reduces the inter-die distance from an otherwise direct transverse circuit routing between the longitudinal edges of the dies.

公开(公告)号：US07659191B2

公开(公告)日：2010-02-09

申请号：US11605831

申请日：2006-11-27

申请人： Kai Liu ,  Ming Sun

发明人： Kai Liu ,  Ming Sun

IPC分类号： H01L21/00 ,  H01L21/76 ,  H01L21/30 ,  H01L21/46 ,  H01L21/44

CPC分类号： H01L24/33 ,  H01L23/49582 ,  H01L24/83 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/32506 ,  H01L2224/83801 ,  H01L2224/83894 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/01014 ,  H01L2924/00

摘要： A direct gold/silicon eutectic die bonding method is disclosed. The method includes the steps of gold plating a die bonding pad, grinding a wafer to a desired thickness, dicing the wafer after the grinding step, picking a die, and attaching the die to the die bonding pad at a temperature above the gold/silicon eutectic temperature. For thinner wafers, a dicing before grinding process is employed.

摘要翻译： 公开了一种直接的金/硅共晶裸片接合方法。 该方法包括以下步骤：将晶片接合焊盘镀金，将晶片研磨至所需厚度，在研磨步骤之后切割晶片，挑选模具，以及在高于金/硅的温度下将模具附接至芯片焊盘 共晶温度。 对于较薄的晶片，采用在研磨过程之前的切割。

公开(公告)号：US20090237837A1

公开(公告)日：2009-09-24

申请号：US12051332

申请日：2008-03-19

申请人： Nurul Amin ,  Ibro Tabakovic ,  Eric S. Linville ,  Ming Sun

发明人： Nurul Amin ,  Ibro Tabakovic ,  Eric S. Linville ,  Ming Sun

IPC分类号： G11B5/33 ,  B05D1/36 ,  C23C16/40

CPC分类号： G11B5/3163 ,  G11B5/3133 ,  Y10T29/49043 ,  Y10T29/49044 ,  Y10T29/49046 ,  Y10T29/49048 ,  Y10T29/49052

摘要： A method of fabricating a recording head includes depositing an insulator material onto at least a portion of a first member, wherein the insulator material forms an insulator film having a film thickness. The method further includes depositing a writer pole material onto the insulator film, wherein the writer pole material forms a writer pole member, and wherein the insulator film is between the writer pole member and a contact layer. Further, in some embodiments, the film thickness determines the distance between the writer pole member and the first contact member and also determines the distance between the writer pole member and the second contact member.

摘要翻译： 制造记录头的方法包括将绝缘体材料沉积在第一构件的至少一部分上，其中绝缘体材料形成具有膜厚度的绝缘膜。 该方法还包括将写入极材料沉积到绝缘膜上，其中写极极材料形成写极极部件，并且其中绝缘膜位于写磁极部件和接触层之间。 此外，在一些实施例中，膜厚决定了写入器极构件和第一接触构件之间的距离，并且还确定了写入器极构件和第二接触构件之间的距离。

公开(公告)号：US20090233403A1

公开(公告)日：2009-09-17

申请号：US12474089

申请日：2009-05-28

申请人： Kai Liu ,  Xiaotian Zhang ,  Ming Sun ,  Leeshawn Luo

发明人： Kai Liu ,  Xiaotian Zhang ,  Ming Sun ,  Leeshawn Luo

IPC分类号： H01L21/60

CPC分类号： H01L24/48 ,  H01L23/3107 ,  H01L23/4952 ,  H01L23/49562 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/45 ,  H01L24/49 ,  H01L24/83 ,  H01L2224/04042 ,  H01L2224/05555 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/48799 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/49431 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/83851 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0781 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/0665 ,  H01L2924/00012

摘要： A DFN semiconductor package includes a leadframe having a die bonding pad formed integrally with a drain lead, a gate lead and a source lead, a die coupled to the die bonding pad, a die source bonding area coupled to the source lead and a die gate bonding area coupled to the gate lead, and an encapsulant at least partially covering the die, drain lead, gate lead and source lead.

摘要翻译： DFN半导体封装包括引线框架，其具有与漏极引线，栅极引线和源极引线一体形成的管芯焊接焊盘，耦合到管芯焊接焊盘的管芯，耦合到源极引线的管芯源极接合区域和管芯栅极 键合区域，以及密封剂，其至少部分地覆盖晶片，漏极引线，栅极引线和源极引线。

公开(公告)号：US20080238599A1

公开(公告)日：2008-10-02

申请号：US11729311

申请日：2007-03-27

申请人： Francois Hebert ,  Ming Sun

发明人： Francois Hebert ,  Ming Sun

IPC分类号： H01F17/04 ,  H01F27/28

CPC分类号： H01L23/645 ,  H01L23/5227 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/1902 ,  H01L2924/3025 ,  Y10T29/4902 ,  Y10T29/49075 ,  H01L2924/00 ,  H01L2224/0401

摘要： A chip scale power converter package having an inductor substrate and a power integrated circuit flipped onto the inductor substrate is disclosed. The inductor substrate includes a high resistivity substrate having a planar spiral inductor formed thereon.

摘要翻译： 公开了一种具有电感器基板和翻转到电感器基板上的功率集成电路的芯片级功率转换器封装。 电感器基板包括其上形成有平面螺旋电感器的高电阻率基板。

公开(公告)号：US20080207094A1

公开(公告)日：2008-08-28

申请号：US11712846

申请日：2007-02-28

申请人： Tao Feng ,  Ming Sun

发明人： Tao Feng ,  Ming Sun

IPC分类号： B24B1/00 ,  B05D1/00 ,  B24B41/06

CPC分类号： B24B7/228 ,  B24B41/06 ,  B28D5/0011 ,  B28D5/0052 ,  H01L24/06 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/06181 ,  H01L2224/16225 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2224/03 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A method and apparatus for ultra thin wafer backside processing are disclosed. The apparatus includes an outer ring holding a high temperature grinding and/or dicing tape to form a support structure. An ultra thin wafer or diced wafer is adhered to the tape within the ring for wafer backside processing. The wafer backside processing includes ion implantation, annealing, etching, sputtering and evaporation while the wafer is in the support structure. Alternative uses of the support structure are also disclosed including the fabrication of dies having metalized side walls.

摘要翻译： 公开了一种用于超薄晶片背面处理的方法和装置。 该装置包括保持高温研磨和/或切割胶带以形成支撑结构的外圈。 超薄晶片或切片晶片粘附在环内用于晶片背面处理的带子上。 晶片背面处理包括离子注入，退火，蚀刻，溅射和蒸发，而晶片处于支撑结构中。 还公开了支撑结构的替代用途，包括制造具有金属化侧壁的模具。

公开(公告)号：US07394151B2

公开(公告)日：2008-07-01

申请号：US11058913

申请日：2005-02-15

申请人： Leeshawn Luo ,  Kai Liu ,  Ming Sun ,  Xiao Tian Zhang

发明人： Leeshawn Luo ,  Kai Liu ,  Ming Sun ,  Xiao Tian Zhang

IPC分类号： H01L23/48

CPC分类号： H01L21/568 ,  H01L23/3107 ,  H01L23/4334 ,  H01L23/49524 ,  H01L24/40 ,  H01L24/73 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/73253 ,  H01L2224/73255 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/37099 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A semiconductor package and method for making a semiconductor package are disclosed. The semiconductor package has a top surface and a mounting surface and includes a die, a conducting connecting material, a plating material and an insulating material. The die has a processed surface facing towards the mounting surface of the semiconductor package. Exposed metal connections are at the processed surface of the die. The conducting connecting material is disposed on the exposed metal connections. The plating material is in contact with the conducting connecting material. The insulating material is formed around the conducting connecting material, and the plating material extends to the exterior of the insulating material.

公开(公告)号：US20070231954A1

公开(公告)日：2007-10-04

申请号：US11396404

申请日：2006-03-31

申请人： Kai Liu ,  Ming Sun

发明人： Kai Liu ,  Ming Sun

IPC分类号： H01L21/00

CPC分类号： H01L24/27 ,  H01L23/49513 ,  H01L23/49582 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/04026 ,  H01L2224/274 ,  H01L2224/29101 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/32506 ,  H01L2224/83801 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01033 ,  H01L2924/01043 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/01014 ,  H01L2924/00

摘要： A gold/silicon eutectic die bonding method is disclosed. The method includes the steps of 1) vacuum evaporating a layer of titanium to a silicon wafer backside, the titanium layer having a thickness less than 200 Å, 2) immediately vacuum evaporating a layer of gold onto the titanium layer, the gold layer having a thickness in the range of 0.5 to 1.5 microns, 3) dicing the wafer, and 4) mounting the die onto a substrate at a eutectic temperature to form a gold/silicon eutectic alloy bond.

摘要翻译： 公开了一种金/硅共晶晶片接合方法。 该方法包括以下步骤：1）将钛层真空蒸发到硅晶片背面，钛层的厚度小于200; 2）立即将一层金层真空蒸发到钛层上，金层具有 厚度在0.5至1.5微米的范围内，3）切割晶片，以及4）以共晶温度将模具安装在基板上以形成金/硅共晶合金。

公开(公告)号：US07263396B2

公开(公告)日：2007-08-28

申请号：US10900146

申请日：2004-07-28

申请人： Yunquan Chen ,  Luya Li ,  Rakesh Kumar Sethi ,  Ming Sun ,  Christopher Grant Denny ,  Scott Howard Phillips

发明人： Yunquan Chen ,  Luya Li ,  Rakesh Kumar Sethi ,  Ming Sun ,  Christopher Grant Denny ,  Scott Howard Phillips

IPC分类号： A61B5/00

CPC分类号： A61B5/14552 ,  A61B5/6816

摘要： A sensor assembly for monitoring physiological characteristics interfaces to a subject's ear. The sensor assembly has a projection that projects into the subject's concha. The projection may have a notch to accommodate the subject's anti-tragus. A clip connected to the projection holds a sensor against the subject's lobule. The sensor may comprise a pulse-oximetry-type sensor.

摘要翻译： 用于监测生理特征的传感器组件与受试者的耳朵接口。 传感器组件具有投影到被检者的外观中的突出部。 该投影可以具有凹口以适应受试者的反耳屏。 连接到突起的夹子将传感器保持在对象的小叶上。 传感器可以包括脉搏血氧测定型传感器。