公开(公告)号：US20080251925A1

公开(公告)日：2008-10-16

申请号：US12142829

申请日：2008-06-20

申请人： Mou-Shiung Lin ,  CHIU-MING CHOU ,  CHIEN-KANG CHOU

发明人： Mou-Shiung Lin ,  CHIU-MING CHOU ,  CHIEN-KANG CHOU

IPC分类号： H01L23/48

CPC分类号： H01L21/768 ,  H01L21/76804 ,  H01L21/76838 ,  H01L21/7685 ,  H01L21/76885 ,  H01L23/522 ,  H01L23/5222 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5228 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/5329 ,  H01L23/60 ,  H01L27/0676 ,  H01L27/08 ,  H01L28/10 ,  H01L28/20 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/16225 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/15174 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/013 ,  H01L2924/00014

摘要： The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick, wide metal lines may be used for long signal paths and can also be used for power buses or power planes, clock distribution networks, critical signal, and re-distribution of I/O pads.

摘要翻译： 本发明在完成的半导体晶片的顶部上添加一层或多层厚的聚合物电介质和一层或多层厚的宽金属线，后钝化。 厚的宽金属线可用于长信号路径，也可用于电力总线或电源平面，时钟分配网络，关键信号和I / O焊盘的重新分配。

公开(公告)号：US07417317B2

公开(公告)日：2008-08-26

申请号：US11818028

申请日：2007-06-13

申请人： Mou-Shiung Lin ,  Chiu-Ming Chou ,  Chien-Kang Chou

发明人： Mou-Shiung Lin ,  Chiu-Ming Chou ,  Chien-Kang Chou

IPC分类号： H01L23/48

CPC分类号： H01L23/62 ,  H01L23/3192 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53252 ,  H01L27/0251 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/00

摘要： A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric and a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide post-passivation interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick passivation interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

摘要翻译： 提供了一种创建互连线的方法。 细线互连提供在已经在衬底的表面中或其上形成的半导体电路的第一绝缘层中。 在电介质层上沉积钝化层，并在钝化层的表面上形成厚的第二电介质层。 在厚的第二层电介质中产生厚而宽的后钝化互连线。 也可以消除第一层电介质，在已​​经沉积在衬底的表面上的钝化层的表面上产生宽厚的钝化互连网络。

公开(公告)号：US07372161B2

公开(公告)日：2008-05-13

申请号：US11017145

申请日：2004-12-20

申请人： Mou-Shiung Lin ,  Chiu-Ming Chou ,  Chien-Kang Chou

发明人： Mou-Shiung Lin ,  Chiu-Ming Chou ,  Chien-Kang Chou

IPC分类号： H01L23/45

CPC分类号： H01L23/60 ,  H01L23/5286 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric and a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide post-passivation interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick passivation interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

公开(公告)号：US20060091540A1

公开(公告)日：2006-05-04

申请号：US11262182

申请日：2005-10-28

申请人： Chiu-Ming Chou ,  Chien-Kang Chou ,  Ching-San Lin ,  Mou-Shiung Lin

发明人： Chiu-Ming Chou ,  Chien-Kang Chou ,  Ching-San Lin ,  Mou-Shiung Lin

IPC分类号： H01L23/48

CPC分类号： H01L24/06 ,  H01L21/76801 ,  H01L24/12 ,  H01L2224/0401 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01079 ,  H01L2924/05042 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00

摘要： The invention provides a semiconductor chip comprising a semiconductor substrate comprising a MOS device, an interconnecting structure over said semiconductor substrate, and a metal bump over said MOS device, wherein said metal bump has more than 50 percent by weight of gold and has a height of between 8 and 50 microns.

摘要翻译： 本发明提供一种半导体芯片，其包括半导体衬底，该半导体衬底包括MOS器件，在所述半导体衬底上的互连结构以及在所述MOS器件上方的金属凸块，其中所述金属凸块具有大于50重量％的金， 介于8和50微米之间。

公开(公告)号：US20060063371A1

公开(公告)日：2006-03-23

申请号：US10948020

申请日：2004-09-23

申请人： Mou-Shiung Lin ,  Chiu-Ming Chou ,  Chien-Kang Chou

发明人： Mou-Shiung Lin ,  Chiu-Ming Chou ,  Chien-Kang Chou

IPC分类号： H01L21/4763

CPC分类号： H01L21/768 ,  H01L21/76804 ,  H01L21/76838 ,  H01L21/7685 ,  H01L21/76885 ,  H01L23/522 ,  H01L23/5222 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5228 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/5329 ,  H01L23/60 ,  H01L27/0676 ,  H01L27/08 ,  H01L28/10 ,  H01L28/20 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/16225 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/15174 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/013 ,  H01L2924/00014

摘要： The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick, wide metal lines may be used for long signal paths and can also be used for power buses or power planes, clock distribution networks, critical signal, and re-distribution of I/O pads.

公开(公告)号：US20060049525A1

公开(公告)日：2006-03-09

申请号：US11017169

申请日：2004-12-20

申请人： Mou-Shiung Lin ,  Chiu-Ming Chou ,  Chien-Kang Chou

发明人： Mou-Shiung Lin ,  Chiu-Ming Chou ,  Chien-Kang Chou

IPC分类号： H01L23/52

CPC分类号： H01L23/3171 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5228 ,  H01L23/5329 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/16265 ,  H01L2924/01019 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/30105 ,  H01L2924/014

摘要： A system and method for forming post passivation metal structures is described. Metal interconnections and high quality electrical components, such as inductors, transformers, capacitors, or resistors are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer.

摘要翻译： 描述了用于形成后钝化金属结构的系统和方法。 金属互连和高质量的电气部件，例如电感器，变压器，电容器或电阻器形成在钝化层上，或者在钝化层上的厚层聚合物上。

公开(公告)号：US20090146305A1

公开(公告)日：2009-06-11

申请号：US12370617

申请日：2009-02-13

申请人： Mou-Shiung Lin ,  Chiu-Ming Chou ,  Chien-Kang Chou

发明人： Mou-Shiung Lin ,  Chiu-Ming Chou ,  Chien-Kang Chou

IPC分类号： H01L23/538

CPC分类号： H01L23/5283 ,  H01L23/5286 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/60 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05083 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05187 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/01074 ,  H01L2924/04953

摘要： A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric and a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide post-passivation interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick passivation interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

摘要翻译： 提供了一种创建互连线的方法。 细线互连提供在已经在衬底的表面中或其上形成的半导体电路的第一绝缘层中。 在电介质层上沉积钝化层，并在钝化层的表面上形成厚的第二电介质层。 在厚的第二层电介质中产生厚而宽的后钝化互连线。 也可以消除第一层电介质，在已​​经沉积在衬底表面上的钝化层的表面上产生宽的厚钝化互连网络。

公开(公告)号：US20090104769A1

公开(公告)日：2009-04-23

申请号：US12276419

申请日：2008-11-24

申请人： Wen-Chieh Lee ,  Mou-Shiung Lin ,  Chien-Kang Chou ,  Yi-Cheng Liu ,  Chiu-Ming Chou ,  Jin-Yuan Lee

发明人： Wen-Chieh Lee ,  Mou-Shiung Lin ,  Chien-Kang Chou ,  Yi-Cheng Liu ,  Chiu-Ming Chou ,  Jin-Yuan Lee

IPC分类号： H01L21/283

CPC分类号： H01L23/3114 ,  H01L23/5227 ,  H01L23/525 ,  H01L24/05 ,  H01L24/10 ,  H01L24/13 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05624 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01009 ,  H01L2924/01011 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2224/45099 ,  H01L2924/00

摘要： A method for fabricating a circuitry component includes providing a semiconductor substrate, a first coil over said semiconductor substrate, a passivation layer over said first coil; and depositing a second coil over said passivation layer and over said first coil. Said second coil may be deposited by forming a first metal layer over said passivation layer, forming a pattern defining layer over said first metal layer, a first opening in said pattern defining layer exposing said first metal layer, forming a second metal layer over said first metal layer exposed by said first opening, removing said pattern defining layer, and removing said first metal layer not under said second metal layer.

摘要翻译： 一种用于制造电路部件的方法包括提供半导体衬底，在所述半导体衬底上的第一线圈，在所述第一线圈上方的钝化层; 以及在所述钝化层上并在所述第一线圈上方沉积第二线圈。 所述第二线圈可以通过在所述钝化层上形成第一金属层而形成，在所述第一金属层上形成图案限定层，所述图案限定层中的第一开口暴露所述第一金属层，在所述第一金属层上形成第二金属层 由所述第一开口暴露的金属层，去除所述图案限定层，以及去除不在所述第二金属层下方的所述第一金属层。

公开(公告)号：US20080251924A1

公开(公告)日：2008-10-16

申请号：US12142825

申请日：2008-06-20

申请人： Mou-Shiung Lin ,  CHIU-MING CHOU ,  CHIEN-KANG CHOU

发明人： Mou-Shiung Lin ,  CHIU-MING CHOU ,  CHIEN-KANG CHOU

IPC分类号： H01L23/522

CPC分类号： H01L23/62 ,  H01L23/3192 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53252 ,  H01L27/0251 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/00

摘要： A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric and a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide post-passivation interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick passivation interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

摘要翻译： 提供了一种创建互连线的方法。 细线互连提供在已经在衬底的表面中或其上形成的半导体电路的第一绝缘层中。 在电介质层上沉积钝化层，并在钝化层的表面上形成厚的第二电介质层。 在厚的第二层电介质中产生厚而宽的后钝化互连线。 也可以消除第一层电介质，在已​​经沉积在衬底表面上的钝化层的表面上产生宽的厚钝化互连网络。

公开(公告)号：US07423346B2

公开(公告)日：2008-09-09

申请号：US10937543

申请日：2004-09-09

申请人： Mou-Shiung Lin ,  Chiu-Ming Chou ,  Chien-Kang Chou

发明人： Mou-Shiung Lin ,  Chiu-Ming Chou ,  Chien-Kang Chou

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L23/5329 ,  H01L23/3171 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5228 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2924/01019 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/30105 ,  H01L2924/014 ,  H01L2924/00012

摘要： A system and method for forming post passivation metal structures is described. Metal interconnections and high quality electrical components, such as inductors, transformers, capacitors, or resistors are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer.

摘要翻译： 描述了用于形成后钝化金属结构的系统和方法。 金属互连和高质量的电气部件，例如电感器，变压器，电容器或电阻器形成在钝化层上，或者在钝化层上的厚层聚合物上。