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117 条记录 (耗时 0.026 秒)

    Selective high k dielectrics removal
    61.
    发明授权
    Selective high k dielectrics removal 失效
    选择性高k电介质去除

    公开(公告)号：US06818516B1

    公开(公告)日：2004-11-16

    申请号：US10629496

    申请日：2003-07-29

    申请人： Wai Lo ,  Hong Lin ,  Shiqun Gu ,  James R. B. Elmer

    发明人： Wai Lo ,  Hong Lin ,  Shiqun Gu ,  James R. B. Elmer

    IPC分类号： H01L21336

    CPC分类号： H01L29/6659 ,  H01L21/31111

    摘要： A method of forming a gate structure in an integrated circuit on a substrate. A high k layer is formed on the substrate, and a gate electrode layer is formed on the high k layer. The gate electrode layer is the patterned. LDD regions are formed using an ion implantation process, thereby creating damaged portions of the high k layer. A first portion of the damaged portions of the high k layer are removed, thereby defining a gate structure, and leaving remaining portions of the damaged portions of the high k layer. Sidewall spacers are formed adjacent the gate structure. Source/drain regions are formed using an ion implantation process, thereby further damaging the remaining portions of the damaged portions of the high k layer. The remaining portions of the damaged portions of the high k layer are then removed.

    摘要翻译： 在基板上的集成电路中形成栅极结构的方法。 在基板上形成高k层，在高k层上形成栅电极层。 栅极电极层是图案化的。 使用离子注入工艺形成LDD区域，从而产生高k层的损坏部分。 去除高k层的损坏部分的第一部分，从而限定栅极结构，并留下高k层的损坏部分的剩余部分。 侧壁间隔件形成在栅极结构附近。 使用离子注入工艺形成源极/漏极区，从而进一步损坏高k层的损伤部分的剩余部分。 然后去除高k层的损坏部分的剩余部分。

    Method of reducing process plasma damage using optical spectroscopy
    62.
    发明授权
    Method of reducing process plasma damage using optical spectroscopy 有权
    使用光谱法降低工艺等离子体损伤的方法

    公开(公告)号：US06673200B1

    公开(公告)日：2004-01-06

    申请号：US10195775

    申请日：2002-07-12

    申请人： Shiqun Gu ,  Peter Gerard McGrath ,  Ryan Tadashi Fujimoto

    发明人： Shiqun Gu ,  Peter Gerard McGrath ,  Ryan Tadashi Fujimoto

    IPC分类号： H01L2100

    CPC分类号： H01L22/34 ,  H01J37/32935 ,  H01J37/32972 ,  H01L21/67069 ,  H01L21/67253 ,  Y10T156/1734

    摘要： Optical emission spectra from a test wafer during a plasma process are measured using a spectrometer. The plasma charging voltage retained by (detected by) the test wafer is measured after the process step is completed. The emission spectra are correlated with the plasma charging voltage to identify the species contributing to the plasma charging voltage. The optical emission spectra are monitored in real time to optimize the plasma process to prevent plasma charging damage. The optical emission spectra are also monitored to control the plasma process drift.

    摘要翻译： 使用光谱仪测量等离子体处理期间来自测试晶片的光发射光谱。 在处理步骤完成之后测量由测试晶片（由检测到的）保持的等离子体充电电压。 发射光谱与等离子体充电电压相关，以识别有助于等离子体充电电压的物质。 实时监测光发射光谱，以优化等离子体处理以防止等离子体充电损坏。 还监测光发射光谱以控制等离子体工艺漂移。

    Load balancing scheme in multiple channel DRAM systems
    63.
    发明授权
    Load balancing scheme in multiple channel DRAM systems 有权
    多通道DRAM系统中的负载均衡方案

    公开(公告)号：US09268720B2

    公开(公告)日：2016-02-23

    申请号：US12872282

    申请日：2010-08-31

    申请人： Feng Wang ,  Shiqun Gu ,  Jonghae Kim ,  Matthew Michael Nowak

    发明人： Feng Wang ,  Shiqun Gu ,  Jonghae Kim ,  Matthew Michael Nowak

    IPC分类号： G06F13/16 ,  G06F12/06

    CPC分类号： G06F13/1647 ,  G06F12/0607 ,  G06F13/1642 ,  G06F13/1657 ,  G06F2213/0064

    摘要： A load balancing in a multiple DRAM system comprises interleaving memory data across two or more memory channels. Access to the memory channels is controlled by memory controllers. Bus masters are coupled to the memory controllers via an interconnect system and memory requests are transmitted from the bus masters to the memory controller. If congestion is detected in a memory channel, congestion signals are generated and transmitted to the bus masters. Memory requests are accordingly withdrawn or rerouted to less congested memory channels based on the congestion signals.

    摘要翻译： 多个DRAM系统中的负载平衡包括跨两个或多个存储器通道交织存储器数据。 内存通道的访问由内存控制器控制。 总线主机通过互连系统耦合到存储器控制器，并且存储器请求从总线主机传送到存储器控制器。 如果在存储器通道中检测到拥塞，则产生拥塞信号并将其发送到总线主机。 因此，基于拥塞信号，存储器请求被相应地撤回或重新路由到较不拥塞的存储器通道。

    LOW-K DIELECTRIC PROTECTION SPACER FOR PATTERNING THROUGH SUBSTRATE VIAS THROUGH A LOW-K WIRING LAYER
    68.
    发明申请
    LOW-K DIELECTRIC PROTECTION SPACER FOR PATTERNING THROUGH SUBSTRATE VIAS THROUGH A LOW-K WIRING LAYER 有权
    低K电介质保护间隔板，用于通过低K布线层通过基板VIAS

    公开(公告)号：US20130113068A1

    公开(公告)日：2013-05-09

    申请号：US13588438

    申请日：2012-08-17

    申请人： Vidhya Ramachandran ,  Shiqun Gu

    发明人： Vidhya Ramachandran ,  Shiqun Gu

    IPC分类号： H01L23/48 ,  H01L21/768

    CPC分类号： H01L21/76898 ,  H01L21/76831 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A low-K value dielectric protection spacer for patterning through substrate vias (TSVs) through a low-K value wiring layer. A method for forming a low-K value dielectric protection spacer includes etching a via opening through a low-K value dielectric interconnect layer. A protective layer is deposited in the via opening and on the low-K value dielectric interconnect layer. At least a portion of the protective layer is etched from the bottom of the via opening and from a horizontal surface of the low-K value dielectric interconnect layer. The etching leaving a protective sidewall spacer on a sidewall of the via opening. A through substrate via is etched through the bottom of the via opening and through the semiconductor substrate. The through substrate via is filled with a conductive material.

    摘要翻译： 低K值介电保护间隔物，用于通过低K值布线层通过衬底通孔（TSV）进行构图。 形成低K值介电保护间隔物的方法包括通过低K值电介质互连层蚀刻通孔。 保护层沉积在通孔开口和低K值电介质互连层上。 保护层的至少一部分从通孔开口的底部和低K值电介质互连层的水平表面被蚀刻。 蚀刻在通孔开口的侧壁上留下保护性侧壁间隔物。 穿通基板通孔被蚀刻穿过通孔开口的底部并穿过半导体基板。 直通基板通孔用导电材料填充。

    Non-Uniform Interleaving Scheme In Multiple Channel DRAM System
    70.
    发明申请
    Non-Uniform Interleaving Scheme In Multiple Channel DRAM System 审中-公开
    多通道DRAM系统中的非均匀交织方案

    公开(公告)号：US20120054455A1

    公开(公告)日：2012-03-01

    申请号：US12872458

    申请日：2010-08-31

    申请人： Feng Wang ,  Shiqun Gu ,  Jonghae Kim ,  Matthew Michael Nowak

    发明人： Feng Wang ,  Shiqun Gu ,  Jonghae Kim ,  Matthew Michael Nowak

    IPC分类号： G06F12/06

    CPC分类号： G06F13/1647 ,  G06F12/0607

    摘要： A non-uniform interleaving scheme in a multiple channel DRAM system comprises associating memory data with a memory address, associating address zones to predetermined ranges of memory addresses and associating predetermined interleaving granularities with the address zones. Memory data is interleaved across two or more memory channels such that a predetermined interleaving granularity is applied to each address zone.

    摘要翻译： 多通道DRAM系统中的非均匀交织方案包括将存储器数据与存储器地址相关联，将地址区域与预定范围的存储器地址相关联，并将预定的交织粒度与地址区域相关联。 存储器数据在两个或更多个存储器通道之间交错，使得预定的交织粒度被应用于每个地址区。