公开(公告)号：US09721860B2

公开(公告)日：2017-08-01

申请号：US14534254

申请日：2014-11-06

Applicant: Texas Instruments Incorporated

Inventor： Osvaldo Jorge Lopez ,  Jonathan Almeria Noquil ,  Tom Grebs ,  Simon John Molloy

IPC: H01L23/13 ,  H01L23/14 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/147 ,  H01L21/481 ,  H01L21/4846 ,  H01L23/13 ,  H01L23/3738 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/06181 ,  H01L2224/32225 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1425 ,  H01L2924/15153 ,  H01L2924/157

Abstract: A packaged transistor device (100) comprises a semiconductor chip (101) including a transistor with terminals distributed on the first and the opposite second chip side; and a slab (110) of low-grade silicon (l-g-Si) configured as a ridge (111) framing a depression including a recessed central area suitable to accommodate the chip, the ridge having a first surface in a first plane and the recessed central area having a second surface in a second plane spaced from the first plane by a depth (112) at least equal to the chip thickness, the ridge covered by device terminals (120; 121) connected to attachment pads in the central area having the terminals of the first chip side attached so that the terminals (103) of the opposite second chip side are co-planar with the device terminals on the slab ridge.

公开(公告)号：US09640519B2

公开(公告)日：2017-05-02

申请号：US14737072

申请日：2015-06-11

Applicant: Texas Instruments Incorporated

Inventor： Osvaldo Jorge Lopez ,  Walter Hans Paul Schroen ,  Jonathan Almeria Noquil ,  Thomas Eugene Grebs ,  Simon John Molloy

IPC: H01L25/16 ,  H01L31/028 ,  H01L31/042 ,  H01L31/0216 ,  H01L27/082 ,  H01L27/088 ,  H01L31/18 ,  H01L31/02 ,  H01L25/00 ,  H01L23/053 ,  H01L23/06 ,  H01L23/13 ,  H01L23/14 ,  H01L21/50 ,  H01L23/00 ,  H01L25/18 ,  H01L29/06 ,  H01L23/498

CPC classification number: H01L25/167 ,  H01L21/50 ,  H01L23/053 ,  H01L23/06 ,  H01L23/13 ,  H01L23/147 ,  H01L23/49844 ,  H01L24/83 ,  H01L25/18 ,  H01L25/50 ,  H01L27/082 ,  H01L27/088 ,  H01L29/0657 ,  H01L31/02008 ,  H01L31/02168 ,  H01L31/028 ,  H01L31/042 ,  H01L31/1804 ,  H01L31/1868 ,  H01L2224/83851 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/04642 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/10155 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/1425 ,  H01L2924/1427 ,  H01L2924/15

Abstract: A self-powered electronic system comprises a first chip (401) of single-crystalline semiconductor embedded in a second chip (302) of single-crystalline semiconductor shaped as a container bordered by ridges. The assembled chips are nested and form an electronic device assembled, in turn, in a slab of weakly p-doped low-grade silicon shaped as a container (330) bordered by ridges (331). The flat side (335) of the slab includes a heavily n-doped region (314) forming a pn-junction (315) with the p-type bulk. A metal-filled deep silicon via (350) through the p-type ridge (331) connects the n-region with the terminal (322) on the ridge surface as cathode of the photovoltaic cell with the p-region as anode. The voltage across the pn-junction serves as power source of the device.

公开(公告)号：US20160218054A1

公开(公告)日：2016-07-28

申请号：US15090176

申请日：2016-04-04

Applicant: Texas Instruments Incorporated

Inventor： Osvaldo Jorge Lopez ,  Jonathan Almeria Noquil

IPC: H01L23/495 ,  H02M3/155

CPC classification number: H01L23/49575 ,  H01L21/563 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49548 ,  H01L23/49551 ,  H01L23/49562 ,  H01L23/49568 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L25/072 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/3716 ,  H01L2224/37599 ,  H01L2224/40245 ,  H01L2224/45015 ,  H01L2224/48106 ,  H01L2224/48108 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49173 ,  H01L2224/73221 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1425 ,  H01L2924/1426 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/181 ,  H02M3/155 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/20752 ,  H01L2924/00012 ,  H01L2924/01028 ,  H01L2224/05599

Abstract: A power supply system has a leadframe with leads and a pad. The pad surface facing a circuit board has a portion recessed with a depth and an outline suitable for attaching side-by-side the sync and the control FET semiconductor chips. The input terminal of the control FET and the grounded output terminal of the sync FET are coplanar with the un-recessed portion of the pad (switch node terminal) so that all terminals can be directly attached to contacts of a circuit board. A driver-and-control chip is vertically stacked to the opposite pad surface and encapsulated in a packaging compound.

Abstract translation: 电源系统具有带引线和焊盘的引线框架。 面对电路板的焊盘表面具有凹陷的部分，其深度和轮廓适合于并置并联和控制FET半导体芯片。 控制FET的输入端子和同步FET的接地输出端子与焊盘（开关节点端子）的未凹入部分共面，使得所有端子可以直接附接到电路板的触点。 驱动器和控制芯片垂直地堆叠到相对的焊盘表面并且封装在封装复合体中。

公开(公告)号：US09373571B2

公开(公告)日：2016-06-21

申请号：US14938387

申请日：2015-11-11

Applicant: Texas Instruments Incorporated

Inventor： Marie Denison ,  Brian Ashley Carpenter ,  Osvaldo Jorge Lopez ,  Juan Alejandro Herbsommer ,  Jonathan Noquil

IPC: H01L25/18 ,  H01L23/495 ,  H01L23/00 ,  H01L21/50 ,  H01L25/065 ,  H01L25/07 ,  H01L25/16 ,  H01L25/00 ,  H01L21/56 ,  H01L23/498

CPC classification number: H01L23/49575 ,  H01L21/50 ,  H01L21/561 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49838 ,  H01L24/29 ,  H01L24/32 ,  H01L24/34 ,  H01L24/36 ,  H01L24/37 ,  H01L24/38 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/84 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/072 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/29101 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40139 ,  H01L2224/40145 ,  H01L2224/40245 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/84801 ,  H01L2224/8484 ,  H01L2224/8485 ,  H01L2924/00014 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01028 ,  H01L2924/014 ,  H01L2924/20752

Abstract: An electronic multi-output device has a substrate including a first pad, a second pad and a plurality of pins. A first chip with a first transistor has a first terminal on one chip surface and a second and third terminals on the opposite chip surface. The first chip with its first terminal is tied to the first pad. A second chip with a second transistor has a first terminal on one chip surface and a second and third terminals on the opposite chip surface. The second chip with its first terminal is tied to the second pad. The second terminals are connected by a discrete first metal clip and a second metal clip to respective substrate pins. A composite third chip has a third and a fourth transistor integrated so that the first terminals of the transistors are on one chip surface. The second terminals are merged into a common terminal. The patterned third terminals are on the opposite chip surface. The first terminals are vertically attached to the first and second metal clips, respectively. The common terminal is connected by a common clip to a substrate pin.

Abstract translation: 电子多输出装置具有包括第一垫，第二垫和多个销的基板。 具有第一晶体管的第一芯片在一个芯片表面上具有第一端子，在相对的芯片表面上具有第二和第三端子。 第一个芯片与第一个终端绑在第一个焊盘上。 具有第二晶体管的第二芯片在一个芯片表面上具有第一端子，在相对的芯片表面上具有第二和第三端子。 具有第一个终端的第二个芯片与第二个焊盘相连。 第二端子通过离散的第一金属夹和第二金属夹连接到相应的衬底引脚。 复合第三芯片具有集成的晶体管的第一端子在一个芯片表面上的第三和第四晶体管。 第二个终端被合并成一个公共终端。 图案化的第三端子在相对的芯片表面上。 第一端子分别垂直地附接到第一和第二金属夹。 公共端子通过公共夹子连接到基板引脚。

公开(公告)号：US20160133535A1

公开(公告)日：2016-05-12

申请号：US14702031

申请日：2015-05-01

Applicant: Texas Instruments Incorporated

Inventor： Osvaldo Jorge Lopez ,  Jonathan Almeria Noquil ,  Thomas Eugene Grebs ,  Simon John Molloy

IPC: H01L23/14 ,  H01L21/78 ,  H01L25/00 ,  H01L25/16 ,  H01L21/48

CPC classification number: H01L23/147 ,  H01L21/481 ,  H01L21/78 ,  H01L23/057 ,  H01L23/08 ,  H01L23/13 ,  H01L25/16 ,  H01L25/165 ,  H01L25/50 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A packaged electronic system comprises a slab (210) of low-grade silicon (l-g-Si) configured as ridges (114) framing a depression of depth (112) including a recessed central area suitable to accommodate semiconductor chips and embedded electrical components, the depth at least equal to the thickness of the chips and the components, the ridge covered by system terminals (209b) connected to attachment pads in the central area; and semiconductor chips (120, 130) having a thickness and terminals on at least one of opposing chip sides, the chips terminals attached to the central area terminals so that the opposite chip side is coplanar with the system terminals on the slab ridge.

Abstract translation: 封装的电子系统包括构造成脊（114）的低等级硅（lg-Si）的板状物（210），其构成包括适于容纳半导体芯片和嵌入式电气部件的凹陷中心区域的深度凹陷（112）， 深度至少等于芯片和部件的厚度，由连接到中心区域中的附接垫的系统端子（209b）覆盖的脊; 和具有厚度的半导体芯片（120,130），并且在相对的芯片侧的至少一个上具有端子，所述芯片端子附接到中心区域端子，使得相对的芯片侧与板条脊上的系统端子共面。

公开(公告)号：US09305852B1

公开(公告)日：2016-04-05

申请号：US14537943

申请日：2014-11-11

Applicant: Texas Instruments Incorporated

Inventor： Osvaldo Jorge Lopez ,  Jonathan Almeria Noquil ,  Thomas Eugene Grebs ,  Simon John Molloy

IPC: H01L23/48 ,  H01L23/06 ,  H01L25/18 ,  H01L25/00 ,  H01L23/053 ,  H01L21/52 ,  H01L23/00 ,  H01L21/82 ,  H01L21/48

CPC classification number: H01L25/0657 ,  H01L21/50 ,  H01L23/053 ,  H01L23/06 ,  H01L23/13 ,  H01L23/147 ,  H01L23/49844 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/071 ,  H01L25/074 ,  H01L25/18 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/06181 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/83851 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/00 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/04642 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/10155 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/1032 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/1037 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1425 ,  H01L2924/1427 ,  H01L2924/15156 ,  H01L2924/157 ,  H01L2224/83

Abstract: An electronic system comprises a first chip (101) of single-crystalline semiconductor including a first electronic device embedded in a second chip (102) of single-crystalline semiconductor shaped as a container having a slab (104) bordered by ridges (103), and including a second electronic device. The nested chips are assembled in a container of low-grade silicon shaped as a slab 130 bordered by retaining walls 131 and including conductive traces and terminals. The first electronic device is connected to the second electronic device by attaching the first chip onto the slab of the second chip; and the first and second electronic devices are connected to the container by embedding the second chip in the container, wherein the nested first and second chips operate as an electronic system and the container operates as the package of the system. For first and second devices as field effect transistors, the system is a power block.

Abstract translation: 电子系统包括单晶半导体的第一芯片（101），其包括第一电子器件，该第一电子器件嵌入单晶半导体的第二芯片（102）中，所述第一芯片形成为具有由脊（103）界定的板（104）的容器， 并且包括第二电子设备。 嵌套芯片组装在低档硅片的容器中，该容器由板状物130与挡板壁131相邻并且包括导电迹线和端子。 第一电子设备通过将第一芯片附接到第二芯片的板上而连接到第二电子设备; 并且第一和第二电子设备通过将第二芯片嵌入容器而连接到容器，其中嵌套的第一和第二芯片作为电子系统操作，并且容器作为系统的封装进行操作。 对于作为场效应晶体管的第一和第二器件，该系统是功率块。

公开(公告)号：US20150221622A1

公开(公告)日：2015-08-06

申请号：US14481204

申请日：2014-09-09

Applicant: Texas Instruments Incorporated

Inventor： Osvaldo Jorge Lopez ,  Jonathan Almeria Noquil

IPC: H01L25/16 ,  H01L23/495 ,  H01L23/31 ,  H01L21/56 ,  H01L25/07 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L23/49575 ,  H01L21/563 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49548 ,  H01L23/49551 ,  H01L23/49562 ,  H01L23/49568 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L25/072 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/3716 ,  H01L2224/37599 ,  H01L2224/40245 ,  H01L2224/45015 ,  H01L2224/48106 ,  H01L2224/48108 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49173 ,  H01L2224/73221 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1425 ,  H01L2924/1426 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/181 ,  H02M3/155 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/20752 ,  H01L2924/00012 ,  H01L2924/01028 ,  H01L2224/05599

Abstract: A power supply system (200) has a QFN leadframe with leads and a pad (201). The pad surface facing a circuit board has a portion recessed with a depth (270) and an outline suitable for attaching side-by-side the sync (210) and the control (220) FET semiconductor chips. The input terminal (220a) of the control FET and the grounded output terminal (210a) of the sync FET are coplanar with the un-recessed portion of the pad (switch node terminal) so that all terminals can be directly attached to contacts of a circuit board. A driver-and-control chip (230) is vertically stacked to the opposite pad surface and encapsulated in a packaging compound (290).

Abstract translation: 电源系统（200）具有带引线的QFN引线框和焊盘（201）。 面对电路板的焊盘表面具有凹陷深度（270）的部分和适合于并联并联（210）和控制（220）FET半导体芯片的轮廓。 控制FET的输入端子（220a）和同步FET的接地输出端子（210a）与焊盘的未凹入部分（开关节点端子）共面，使得所有端子可以直接附接到 电路板。 驱动器和控制芯片（230）垂直地堆叠到相对的焊盘表面并且封装在封装化合物（290）中。