公开(公告)号：US09891927B2

公开(公告)日：2018-02-13

申请号：US14281551

申请日：2014-05-19

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker ,  Stephan Gaskins

IPC: G06F1/00 ,  H04L29/06 ,  G06F9/38 ,  G06F1/32 ,  G06F12/084 ,  G06F13/24 ,  G06F9/44 ,  G06F13/364 ,  G06F12/0808 ,  G06F9/30 ,  G06F12/0875 ,  G06F1/04 ,  G06F1/12 ,  G06F13/42 ,  G06F21/53 ,  G06F21/57 ,  H04L9/08

CPC classification number: G06F9/3885 ,  G06F1/04 ,  G06F1/12 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/30032 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/30087 ,  G06F9/30105 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3861 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4411 ,  G06F9/4418 ,  G06F12/0808 ,  G06F12/084 ,  G06F12/0875 ,  G06F13/24 ,  G06F13/364 ,  G06F13/42 ,  G06F21/53 ,  G06F21/57 ,  G06F2212/452 ,  G06F2212/6028 ,  G06F2212/62 ,  H01L22/34 ,  H04L9/0877 ,  H04L9/0897 ,  Y02B70/12 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/30 ,  Y02D10/10 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/13 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/30 ,  Y02D50/20

Abstract: A microprocessor includes a plurality of processing cores and an uncore random access memory (RAM) readable and writable by each of the plurality of processing cores. Each core of the plurality of processing cores comprises microcode run by the core that implements architectural instructions of an instruction set architecture of the microprocessor. The microcode is configured to both read and write the uncore RAM to accomplish inter-core communication between the plurality of processing cores.

公开(公告)号：US20180032457A1

公开(公告)日：2018-02-01

申请号：US15220077

申请日：2016-07-26

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Helena Deirdre O'Shea ,  Richard Dominic Wietfeldt

IPC: G06F13/364 ,  G06F13/22 ,  G06F13/40 ,  G06F13/24 ,  G06F13/42

CPC classification number: G06F13/364 ,  G06F13/00 ,  G06F13/22 ,  G06F13/24 ,  G06F13/404 ,  G06F13/42 ,  G06F13/4291 ,  Y02D10/14 ,  Y02D10/151

Abstract: Slave initiated interrupts for a communication bus are disclosed. In one aspect, the communication bus is a radio frequency front end (RFFE) bus, and a slave is allowed to indicate to a master on the RFFE bus that the slave has an interrupt condition. On receipt of a slave initiated interrupt, the master may initiate a polling sequence to determine which of a plurality of slaves associated with the RFFE bus initiated the interrupt and process the interrupt accordingly. Continuing the exemplary aspect, the slave may indicate the interrupt condition to the master by driving a clock line of the RFFE bus to a non-idle state. The master may detect this manipulation of the clock line and initiate the polling sequence.

公开(公告)号：US09880953B2

公开(公告)日：2018-01-30

申请号：US14589185

申请日：2015-01-05

Applicant: Tuxera Corporation

Inventor： Bastian Arjun Shajit ,  Szabolcs Szakacsits

IPC: G06F9/00 ,  G06F13/24 ,  G06F9/48 ,  H04L12/26

CPC classification number: G06F13/24 ,  G06F9/4812 ,  H04L43/0888

Abstract: Systems and techniques for managing network processing on a central processing unit including multiple cores are described. Techniques may determine respective resource utilization for one or more processing cores. In one example resource utilization for cores may be determined based on one or more of task utilization time, processor load based on hardware interrupts, cycles spent on processing network packets, utilization based on software interrupts, and idle time. Interrupts may be steered to a core based on resource utilization.

公开(公告)号：US20180024953A1

公开(公告)日：2018-01-25

申请号：US15293307

申请日：2016-10-14

Applicant: Shang-Heng Lin ,  Jiun-Shiue Huang ,  Yu-Hsiang Lee

Inventor： Shang-Heng Lin ,  Jiun-Shiue Huang ,  Yu-Hsiang Lee

IPC: G06F13/40 ,  G06F13/10 ,  G06F13/42

CPC classification number: G06F13/4022 ,  A61B5/7475 ,  G06F13/102 ,  G06F13/24 ,  G06F13/385 ,  G06F13/4282 ,  G06F13/4295

Abstract: A peripheral interface chip and a data transmission method thereof are provided. The peripheral interface chip includes a switching circuit, a universal serial bus (USB) host controller, a keyboard controller and a microprocessor. The switching circuit receives a device identification transmitted from a USB device, and the device identification is used for determining whether the USB device is a keyboard device. When the USB device is the keyboard device, input data of the USB device is transmitted to a controller hub through a first USB interface, the switching circuit, the USB host controller, the microprocessor, the keyboard controller and a low pin count (LPC) interface.

公开(公告)号：US20180024952A1

公开(公告)日：2018-01-25

申请号：US15541393

申请日：2016-01-15

Applicant: NEC Corporation

Inventor： Masahiko TAKAHASHI

IPC: G06F13/28 ,  G06F13/24 ,  G06F13/42

CPC classification number: G06F13/28 ,  G06F13/14 ,  G06F13/24 ,  G06F13/4282 ,  G06F15/17331 ,  G06F2213/0026

Abstract: To realize DMA data transfer between a host computer and another computer even in the case that the host computer and the another computer are each equipped with a CPU, a memory, and so forth independently. A computer communicably connected with a first computer including a first memory and a driver for controlling a device, the computer comprising: the device; and a second memory, wherein a first DMA transfer is executed based on a DMA transfer request received from the driver, a second DMA transfer is executed to transfer data existing at a transfer destination address of the first DMA transfer between the first memory and the second memory, and the transfer destination address is detected as a result of executing the first DMA transfer.

公开(公告)号：US09875136B2

公开(公告)日：2018-01-23

申请号：US14400219

申请日：2013-05-11

Applicant: Indrajith Kuruppu ,  Don Damith Nadishan Colambathanthrige

Inventor： Indrajith Kuruppu ,  Don Damith Nadishan Colambathanthrige

IPC: G06F9/48 ,  G06F13/24

CPC classification number: G06F9/4812 ,  G06F13/24 ,  Y02B70/12 ,  Y02D10/14

Abstract: A novel approach to coordinate processes in a process environment includes establishing a coherent temporal and resource framework for operation of selected processes in order to formulate a basis for coordination. A key aspect of the present innovation includes the novel techniques for coordinating processes including transmission of electromagnetism and transmission of electromagnetic radiation in a process environment by effecting periodic interruptions, based upon the abovementioned coherent temporal and resource framework, while maintaining the required operational and safety procedures.

公开(公告)号：US09874926B2

公开(公告)日：2018-01-23

申请号：US14498319

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： Herbert Hum ,  Eric Sprangle ,  Douglas Carmean ,  Rajesh Kumar

IPC: G06F1/32 ,  G06T1/20 ,  G06F9/50 ,  G06F13/24 ,  G06F9/38 ,  G06F9/46 ,  G06F1/20 ,  G06F12/0875

CPC classification number: G06F1/3293 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/3869 ,  G06F9/461 ,  G06F9/5088 ,  G06F9/5094 ,  G06F12/0875 ,  G06F13/24 ,  G06F2209/5017 ,  G06F2212/452 ,  G06T1/20 ,  Y02B70/10 ,  Y02B70/1425 ,  Y02B70/30 ,  Y02B70/32 ,  Y02D10/122 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D50/20

Abstract: Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system.

公开(公告)号：US09870047B2

公开(公告)日：2018-01-16

申请号：US15192134

申请日：2016-06-24

Applicant: Intel Corporation

Inventor： Andrew J. Herdrich ,  Rameshkumar G. Illikkal ,  Ravishankar Iyer ,  Sadagopan Srinivasan ,  Jaideep Moses ,  Srihari Makineni

IPC: G06F1/32 ,  G06F12/08 ,  H04W88/02 ,  H04W52/02 ,  G06F9/44 ,  G06F13/24 ,  G06F9/50 ,  G06F12/084

CPC classification number: G06F1/3293 ,  G06F1/3206 ,  G06F1/3287 ,  G06F9/4418 ,  G06F9/5094 ,  G06F12/084 ,  G06F13/24 ,  G06F2212/1028 ,  G06F2212/60 ,  G06F2212/62 ,  H04W52/028 ,  H04W88/02 ,  Y02B70/30 ,  Y02B70/32 ,  Y02D10/122 ,  Y02D10/22 ,  Y02D70/00

Abstract: In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.

公开(公告)号：US20180004622A1

公开(公告)日：2018-01-04

申请号：US15703860

申请日：2017-09-13

Applicant: Intel Coproration

Inventor： Jason W. Brandt

IPC: G06F11/34 ,  G06F9/48 ,  G06F11/30 ,  G06F13/24

CPC classification number: G06F11/3466 ,  G06F9/4812 ,  G06F11/3024 ,  G06F13/24

Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for monitoring performance of a processor to manage events. A processor includes a first performance counter to increment upon occurrence of a first type of event in the processor and a second performance counter to increment upon occurrence of a second type of event in the processor. The processor is to reset the second performance counter in response to the first performance counter reaching a first limit.

公开(公告)号：US20170364462A1

公开(公告)日：2017-12-21

申请号：US15639866

申请日：2017-06-30

Applicant: Andium Inc.

Inventor： Jory Schwach ,  Brian Bosak

IPC: G06F13/24

CPC classification number: G06F13/24

Abstract: A real-time operating system (OS) for an embedded system may be configured for asynchronous handling of input and output (I/O) operations. When application code is executing, the OS may be configured to register I/O interrupts and queue I/O operations. When no application code is executing, the OS may be configured to call appropriate interrupt handlers. As result, the OS may maintain the real-time execution that may be required of applications on an embedded system while providing the flexibility and scalability offered by an operating system.