公开(公告)号：US20240145007A1

公开(公告)日：2024-05-02

申请号：US18404690

申请日：2024-01-04

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Huangpeng Zhang ,  Zhichao Du ,  Ke Jiang ,  Cong Luo ,  Daesik Song

IPC: G11C16/10 ,  G06F3/06 ,  G11C16/04 ,  G11C16/08

CPC classification number: G11C16/10 ,  G06F3/0604 ,  G06F3/0655 ,  G06F3/0679 ,  G11C16/0483 ,  G11C16/08 ,  H10B43/27

Abstract: In certain aspects, a memory device includes memory cells, word lines coupled to the memory cells, and a peripheral circuit coupled to the memory cells. The peripheral circuit is coupled to the word lines and configured to apply program pulses to a selected word line of the word lines in a program operation, obtain a number of occurrences of suspensions during the program operation, and determine a limit on a number of program pulses for the program operation based on the number of occurrences of the suspensions during the program operation.

公开(公告)号：US11974425B2

公开(公告)日：2024-04-30

申请号：US17743248

申请日：2022-05-12

Applicant: Zeno Semiconductor, Inc.

Inventor： Yuniarto Widjaja ,  Jin-Woo Han ,  Benjamin S. Louie

IPC: H10B12/00 ,  G11C11/404 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  H01L29/08 ,  H01L29/10 ,  H01L29/36 ,  H01L29/70 ,  H01L29/73 ,  H01L29/732 ,  H01L29/78 ,  H10B12/10 ,  H10B41/35

CPC classification number: H10B12/20 ,  G11C11/404 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3427 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/70 ,  H01L29/73 ,  H01L29/7302 ,  H01L29/7841 ,  H10B12/10 ,  H10B41/35 ,  H01L29/1004 ,  H01L29/732

Abstract: Semiconductor memory cells, array and methods of operating are disclosed. In one instance, a memory cell includes a bi-stable floating body transistor and an access device; wherein the bi-stable floating body transistor and the access device are electrically connected in series.

公开(公告)号：US11971829B2

公开(公告)日：2024-04-30

申请号：US17557428

申请日：2021-12-21

Applicant: SanDisk Technologies LLC

Inventor： Hua-Ling Cynthia Hsu ,  A. Harihara Sravan ,  YenLung Li

IPC: G06F13/16 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  H01L25/065

CPC classification number: G06F13/1668 ,  G06F13/1673 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C11/5671 ,  H01L25/0657 ,  H01L2225/06562

Abstract: For a non-volatile memory that uses hard bit and a soft bit data in error correction operations, an on-the-fly compression scheme is used for the soft bit data. As soft bit data is transferred to a memory's input-output interface, the soft bit data is compressed prior to transmission to the an ECC engine memory controller, while hard bit data is transferred in un-compressed form.

公开(公告)号：US11961570B2

公开(公告)日：2024-04-16

申请号：US16912694

申请日：2020-06-25

Applicant: Vishal Sarin ,  Vikram Kowshik ,  Purval Sule ,  Siraj Fulum Mossa

Inventor： Vishal Sarin ,  Vikram Kowshik ,  Purval Sule ,  Siraj Fulum Mossa

IPC: G11C16/34 ,  G06N3/063 ,  G11C11/54 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24

CPC classification number: G11C16/3459 ,  G06N3/063 ,  G11C11/54 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24 ,  G11C16/0466

Abstract: In one aspect, a method for NOR flash cell-array programming in a neural circuit includes the step of erasing a cell array. The method includes the step of programming a set of reference cells of a reference cell array to a target reference threshold voltage (Vt_ref). The method includes the step of generating, with the reference cells, a current or voltage, reference signal. The method includes the step of using the reference signal to bias the neural cells during verification of program state of the neural cells to achieve their respective target threshold voltages (Vt_cell). The method includes the step of programming a set of neural cells of a neural cell array to their respective target threshold voltages.

公开(公告)号：US11948647B2

公开(公告)日：2024-04-02

申请号：US17902130

申请日：2022-09-02

Applicant: Micron Technology, Inc.

Inventor： Michele Piccardi

IPC: G11C16/00 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/34

CPC classification number: G11C16/30 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3404

Abstract: A first digitally-controlled pump voltage level is established for a charge pump coupled to a wordline of a memory device of a memory sub-system. A determination is made whether a measured digitally-controlled voltage level of the wordline and the first digitally-controlled pump voltage level satisfy a condition. In response to determining that the condition is satisfied, a signal is generated to adjust the first digitally-controlled pump voltage level to a second digitally-controlled pump voltage level.

公开(公告)号：US20240107755A1

公开(公告)日：2024-03-28

申请号：US18534818

申请日：2023-12-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Hsien Chen ,  Chun-Yao Ko ,  Felix Ying-Kit Tsui

IPC: H10B41/35 ,  G11C16/10 ,  H01L29/06 ,  H01L29/66 ,  H01L29/788 ,  H10B41/41 ,  H10B41/42

CPC classification number: H10B41/35 ,  G11C16/10 ,  H01L29/0649 ,  H01L29/66825 ,  H01L29/7883 ,  H10B41/41 ,  H10B41/42 ,  G11C16/30

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor structure including a first well region disposed within a substrate and comprising a first doping type. A conductive structure overlies the first well region. A pair of first doped regions is disposed within the first well region on opposing sides of the conductive structure. The pair of first doped regions comprise a second doping type opposite the first doping type. A pair of second doped regions is disposed within the first well region on the opposing sides of the conductive structure. The pair of second doped regions comprise the second doping type and are laterally offset from the pair of first doped regions by a non-zero distance.

公开(公告)号：US20240104037A1

公开(公告)日：2024-03-28

申请号：US18216543

申请日：2023-06-29

Applicant: Rambus Inc.

Inventor： Scott C. Best

IPC: G06F13/362 ,  G06F13/40 ,  G11C11/408 ,  G11C11/409 ,  G11C11/4096 ,  G11C14/00 ,  G11C16/10 ,  G11C16/26 ,  H01L23/00 ,  H01L23/48 ,  H01L23/50 ,  H01L23/60 ,  H01L25/065 ,  H01L27/02

CPC classification number: G06F13/362 ,  G06F13/4068 ,  G11C11/408 ,  G11C11/409 ,  G11C11/4096 ,  G11C14/0018 ,  G11C16/10 ,  G11C16/26 ,  H01L23/481 ,  H01L23/50 ,  H01L23/60 ,  H01L24/09 ,  H01L25/0652 ,  H01L25/0657 ,  H01L27/0248 ,  H01L23/48 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06503 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/1436 ,  H01L2924/15311

Abstract: This application is directed to a stacked semiconductor device assembly including a plurality of identical stacked integrated circuit (IC) devices. Each IC device further includes a master interface, a channel master circuit, a slave interface, a channel slave circuit, a memory core, and a modal pad configured to receive a selection signal for the IC device to communicate data using one of its channel master circuit or its channel slave circuit. In some implementations, the IC devices include a first IC device and one or more second IC devices. In accordance with the selection signal, the first IC device is configured to communicate read/write data via the channel master circuit of the first IC device, and each of the one or more second IC devices is configured to communicate respective read/write data via the channel slave circuit of the respective second IC device.

公开(公告)号：US11942165B2

公开(公告)日：2024-03-26

申请号：US17725144

申请日：2022-04-20

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Weijun Wan

IPC: G11C16/04 ,  G11C11/56 ,  G11C16/10 ,  G11C16/34

CPC classification number: G11C16/3459 ,  G11C11/5628 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/10

Abstract: A memory device includes memory cells, and a first latch circuit, a second latch circuit, and a third latch circuit, coupled to the memory cells, wherein the first latch circuit is configured to store verification data during a verification operation, the second latch circuit is configured to store failure pattern data during the verification operation, and the third latch circuit is configured to store program data.

公开(公告)号：US11942156B2

公开(公告)日：2024-03-26

申请号：US17671906

申请日：2022-02-15

Applicant: SK hynix Inc.

Inventor： Hyeok Jun Choi ,  Hee Sik Park ,  Seung Geun Jeong

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/3459

Abstract: Provided herein is a memory device for performing a program operation on memory cells. The memory device include a plurality of memory cells configured to store data, a voltage generator configured to apply program voltages to a word line coupled to the plurality of memory cells during a program operation in which the plurality of memory cells are programmed to a plurality of program states, a cell speed determiner configured to determine a program speed of the plurality of memory cells depending on a number of pulses for the program voltages applied to the word line while the program operation is being performed, and a program manager configured to change a condition for remaining program operations depending on the program speed determined by the cell speed determiner.

公开(公告)号：US11942155B2

公开(公告)日：2024-03-26

申请号：US17490097

申请日：2021-09-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Meng-Sheng Chang ,  Chia-En Huang ,  Yih Wang

IPC: G11C5/06 ,  G11C16/10 ,  G11C16/26 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

CPC classification number: G11C16/10 ,  G11C16/26 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/7841

Abstract: A memory system includes a memory array comprising a plurality of memory cells. Each of the memory cells includes a first programming transistor, a second programming transistor, a first reading transistor coupled to the first programming transistor in series, and a second reading transistor coupled to the second programming transistor in series. The memory system includes an authentication circuit operatively coupled to the memory array. The authentication circuit is configured to generate a Physically Unclonable Function (PUF) signature based on respective logic states of the plurality of memory cells. The logic state of each of the plurality of memory cells is determined based on a preceding breakdown of either the corresponding first programming transistor or second programming transistor.