公开(公告)号：US5676853A

公开(公告)日：1997-10-14

申请号：US653071

申请日：1996-05-21

申请人： James J. Alwan

发明人： James J. Alwan

IPC分类号： G03F1/00 ,  H01J9/02 ,  H01L21/033 ,  B05D5/00

CPC分类号： H01J9/025 ,  H01L21/0331 ,  H01L21/0337 ,  Y10S438/945

摘要： A mask and a method for forming a mask on a surface of an underlying layer of material used in semiconductor device manufacturing. The mask is a mixture of mask particles and spacer particles. The spacer particles space the mask particles apart from one another to control the distance and the uniformity of the distribution of mask particles across the surface of the underlying layer. The spacer particles and mask particles have different physical properties that allow the spacer particles to be selectively removed from the surface of the underlying layer. The spacer particles are preferably removed from the surface of the underlying layer by selectively etching the spacer particles from the underlying layer. After the spacer particles are removed from the underlying layer, the mask particles remain on the underlying layer to provide spaced apart mask elements on the surface of the underlying layer.

摘要翻译： 在半导体器件制造中使用的材料的下层的表面上形成掩模的掩模和方法。 掩模是掩模颗粒和间隔物颗粒的混合物。 间隔物颗粒将掩模颗粒彼此分开，以控制掩模颗粒在下层的表面上的分布的距离和均匀性。 间隔物颗粒和掩模颗粒具有不同的物理性质，其允许间隔物颗粒从下层的表面选择性地除去。 通过从下层选择性地蚀刻间隔物颗粒，优选从基底层的表面除去间隔物颗粒。 在将间隔物颗粒从下层除去之后，掩模颗粒保留在下层上，以在下层的表面上提供间隔开的掩模元件。

公开(公告)号：US5654208A

公开(公告)日：1997-08-05

申请号：US436487

申请日：1995-05-08

申请人： Christopher Harris ,  Andrei Konstantinov ,  Erik Janzen

发明人： Christopher Harris ,  Andrei Konstantinov ,  Erik Janzen

IPC分类号： H01L21/22 ,  H01L21/04 ,  H01L21/265 ,  H01L21/318 ,  H01L29/24 ,  H01L29/861

CPC分类号： H01L29/1608 ,  H01L21/0455 ,  H01L21/0465 ,  H01L21/318 ,  H01L29/6606 ,  Y10S148/126 ,  Y10S438/931 ,  Y10S438/945

摘要： The present invention relates to a method for producing a semiconductor device having a semiconductor layer of SiC. The method comprises the steps of a) applying a mask on at least a portion of the SiC layer to coat a first portion of the SiC layer leaving a second portion thereof uncoated, b) applying a heat treatment to the SiC layer, and c) supplying dopants to the SiC layer during the heat treatment for diffusion of the dopants into the SiC layer at the second portion thereof for doping the SiC layer. The mask is made of crystalline AIN as the only component or AIN as a major component of a crystalline alloy constituting the material.

摘要翻译： 本发明涉及一种具有SiC半导体层的半导体器件的制造方法。 该方法包括以下步骤：a）在SiC层的至少一部分上施加掩模，以涂覆SiC层的第一部分，留下未涂覆的第二部分，b）对SiC层进行热处理，以及c） 在用于掺杂SiC层的第二部分期间将掺杂剂扩散到SiC层的热处理期间向SiC层提供掺杂剂。 掩模由结晶AIN作为构成材料的结晶合金的主要成分的唯一成分或AlN。

公开(公告)号：US5641695A

公开(公告)日：1997-06-24

申请号：US538063

申请日：1995-10-02

申请人： Karen E. Moore ,  Charles E. Weitzel

发明人： Karen E. Moore ,  Charles E. Weitzel

IPC分类号： H01L21/04 ,  H01L29/24 ,  H01L29/808 ,  H01L21/265 ,  H01L21/20

CPC分类号： H01L29/1608 ,  H01L29/66068 ,  H01L29/808 ,  Y10S438/931 ,  Y10S438/945

摘要： An implant mask (14) and an etch mask (16) are utilized in forming a silicon carbide JFET (10). A source opening (17) and a drain opening (18) are formed in the masks (14,16). The etch mask (16) is removed, and a source area (19) and a drain area 21 are implanted through the openings (17,18) and source and drain contact (23, 24) are formed. A protective layer (26) is used to form source and drain contacts (23,24). A gate contact (27) is utilized to ensure the gate (28) is self-aligned to the gate contact (27).

摘要翻译： 在形成碳化硅JFET（10）中使用注入掩模（14）和蚀刻掩模（16）。 在所述掩模（14,16）中形成有源极开口（17）和排出开口（18）。 去除蚀刻掩模（16），并且通过开口（17,18）注入源极区域（19）和漏极区域21，并且形成源极和漏极接触（23,24）。 保护层（26）用于形成源极和漏极接触（23,24）。 栅极接触（27）用于确保栅极（28）与栅极接触件（27）自对准。

公开(公告)号：US5561071A

公开(公告)日：1996-10-01

申请号：US532542

申请日：1995-09-25

申请人： Cornelis P. Hollenberg ,  Ernesto di Mauro

发明人： Cornelis P. Hollenberg ,  Ernesto di Mauro

IPC分类号： H01L49/00 ,  C07H21/04 ,  G01N33/53 ,  G01N37/00 ,  G03F1/00 ,  G06N3/12 ,  H01L21/312 ,  H01L21/32 ,  H01L21/50 ,  H01L21/70 ,  H01L21/98 ,  H01L27/28 ,  H01L51/00 ,  H01L51/05 ,  H01L51/30 ,  H01L51/40

CPC分类号： H01L51/0595 ,  B82Y10/00 ,  G06N3/123 ,  H01L21/32 ,  H01L25/50 ,  H01L51/0093 ,  H01L2924/0002 ,  Y10S435/81 ,  Y10S438/944 ,  Y10S438/945

摘要： The invention relates to construction of specific molecular microcircuits by the use of double and single stranded nucleic acids and specific DNA-binding proteins.

摘要翻译： 本发明涉及通过使用双链和单链核酸和特异性DNA结合蛋白构建特定分子微电路。

公开(公告)号：US5468342A

公开(公告)日：1995-11-21

申请号：US234478

申请日：1994-04-28

申请人： James E. Nulty ,  Pamela S. Trammel

发明人： James E. Nulty ,  Pamela S. Trammel

IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L21/306 ,  B44C1/22 ,  C03C15/00

CPC分类号： H01L21/31144 ,  H01L21/31116 ,  H01L21/76816 ,  Y10S438/945

摘要： A method of etching openings in oxide layers is disclosed. A hard mask layer is formed on the oxide layer. The hard mask layer is then patterned by a photoresist layer and an etch is performed to form openings in the hard mask. Next, the patterning layer may be removed and an etch is performed to remove the oxide in the regions defined by the hard mask layer openings. The etch with hard mask has minimized aspect ratio dependency, so that openings of different sizes may be formed simultaneously. An etch that may be carried out with Freon 134a (C.sub.2 H.sub.2 F.sub.4) to provide superior oxide:nitride selectivity is also disclosed. Additionally, the etch may be carried out at high temperature for improved wall profile without loss of selectivity. For deep openings, a two step etch process is disclosed, with a polymer clean step between the etches to remove polymer build up from first etch, and allow the etch to proceed to an increased depth.

摘要翻译： 公开了一种蚀刻氧化物层中的开口的方法。 在氧化物层上形成硬掩模层。 然后通过光致抗蚀剂层对硬掩模层进行构图，并进行蚀刻以在硬掩模中形成开口。 接下来，可以去除图案化层，并且进行蚀刻以去除由硬掩模层开口限定的区域中的氧化物。 具有硬掩模的蚀刻具有最小化的纵横比依赖性，使得可以同时形成不同尺寸的开口。 还公开了可以用氟利昂134a（C 2 H 2 F 4）进行的提供优异的氧化物：氮化物选择性的蚀刻。 此外，蚀刻可以在高温下进行，以改善壁形，而不损失选择性。 对于深开口，公开了两步蚀刻工艺，其中在蚀刻之间的聚合物清洁步骤以从第一次蚀刻中除去聚合物，并允许蚀刻进行到增加的深度。

公开(公告)号：US5340773A

公开(公告)日：1994-08-23

申请号：US960789

申请日：1992-10-14

申请人： Tomio Yamamoto

发明人： Tomio Yamamoto

IPC分类号： C25D3/48 ,  H01L21/28 ,  H01L21/288 ,  H01L21/3205 ,  H01L23/52

CPC分类号： H01L21/2885 ,  Y10S148/105 ,  Y10S438/945

摘要： A method of fabricating a semiconductor device in which first an aluminum film is etched using a photoresist pattern as a mask, and then the patterned aluminum film is used as a mask for plating to form a pattern of gold plating film. In so doing, if a wiring is formed using a plating process, the problems of deformity of the gold plating film due to degradation of a plating solution, short-circuits between the patterns due to cracks in the plating mask, and re-adhering of etched material when etching the electrical current paths used during the electroplating process, and the problem of sideways etching can be solved.

摘要翻译： 一种制造半导体器件的方法，其中首先使用光致抗蚀剂图案作为掩模蚀刻铝膜，然后使用图案化的铝膜作为电镀掩模以形成镀金膜的图案。 这样做时，如果使用电镀工艺形成布线，则由于电镀液的劣化导致的镀金膜变形的问题，由于电镀掩模中的裂纹引起的图案之间的短路以及再次附着 当蚀刻在电镀工艺期间使用的电流路径时蚀刻材料，并且可以解决横向蚀刻的问题。

公开(公告)号：US5275973A

公开(公告)日：1994-01-04

申请号：US24150

申请日：1993-03-01

申请人： Avgerinos V. Gelatos

发明人： Avgerinos V. Gelatos

IPC分类号： H01L21/768 ,  H01L21/283 ,  H01L21/31

CPC分类号： H01L21/76831 ,  H01L21/76879 ,  Y10S438/926 ,  Y10S438/945

摘要： Metallization having a self-aligned diffusion barrier or seed layer is formed in an integrated circuit. In one embodiment of the invention, a sacrificial material (20) is used to define a seed layer (24). A dielectric layer (26) is then formed and the sacrificial material (20) is subsequently removed to expose the underlying seed layer (24). A conductive layer of material (32), such as copper, is then selectively deposited onto the seed layer (24). Because the diffusion barrier or seed layer is self-aligned the metal to metal spacing in an integrated circuit may be reduced. Therefore, integrated circuits having high device packing densities can be fabricated.

摘要翻译： 在集成电路中形成具有自对准扩散阻挡层或种子层的金属化。 在本发明的一个实施例中，牺牲材料（20）用于限定种子层（24）。 然后形成电介质层（26），随后去除牺牲材料（20）以暴露下面的种子层（24）。 然后将诸如铜的材料（32）的导电层选择性地沉积到籽晶层（24）上。 因为扩散阻挡层或种子层是自对准的，所以集成电路中的金属间距可以减小。 因此，可以制造具有高器件封装密度的集成电路。

公开(公告)号：US5173438A

公开(公告)日：1992-12-22

申请号：US656365

申请日：1991-02-13

申请人： Gurtej S. Sandhu

发明人： Gurtej S. Sandhu

IPC分类号： H01L21/266 ,  H01L21/762

CPC分类号： H01L21/266 ,  H01L21/76213 ,  H01L21/76216 ,  Y10S148/105 ,  Y10S438/945

摘要： An improved field implant process is disclosed wherein the field implant is performed after the field oxide isolation structure is fabricated by masking the active surface regions of the substrate with tungsten. The tungsten may be selectively deposited or blanket deposited. The energy of the field implant is controlled and adjusted to produce a maximum number of ions contiguous to a thinnest portion of field oxide with other portions being self-regulating.

摘要翻译： 公开了一种改进的场注入工艺，其中在通过用钨掩蔽衬底的有源表面区域来制造场氧化物隔离结构之后进行场注入。 可以选择性地沉积或覆盖钨。 控制和调整场注入的能量以产生与场氧化物的最薄部分相邻的最大数量的离子，其他部分是自调节的。

公开(公告)号：US5091339A

公开(公告)日：1992-02-25

申请号：US557427

申请日：1990-07-23

申请人： David H. Carey

发明人： David H. Carey

IPC分类号： H01L21/311 ,  H01L21/48 ,  H01L21/768 ,  H01L23/485 ,  H05K3/00 ,  H05K3/10 ,  H05K3/38 ,  H05K3/40 ,  H05K3/42 ,  H05K3/46

CPC分类号： H01L21/76817 ,  H01L21/31144 ,  H01L21/486 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76813 ,  H01L23/485 ,  H05K3/0032 ,  H05K3/0041 ,  H05K3/005 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K2201/0166 ,  H05K2201/09563 ,  H05K2203/0108 ,  H05K2203/025 ,  H05K2203/0554 ,  H05K2203/0574 ,  H05K2203/1189 ,  H05K3/0023 ,  H05K3/0035 ,  H05K3/107 ,  H05K3/388 ,  H05K3/4076 ,  H05K3/422 ,  H05K3/4644 ,  H05K3/4661 ,  Y10S438/94 ,  Y10S438/945

摘要： Channels extending partially through and vias extending completely through an insulating layer in an electrical interconnect such as a substrate or integrated circuit can be formed in a relatively few steps with low cost etching and patterning techniques. The channels and vias can then be filled with an electrical conductor in a relatively few steps. In one embodiment a non-erodible hard mask exposing the vias and channels is placed over a polyimide layer, an erodible soft mask exposing the vias but covering the channels is placed over the hard mask, and a plasma etch is applied. The via regions are etched until the soft mask completely erodes and then both the via and channel regions are etched to provide partially etched channels and fully etched vias. Thereafter a seed layer is deposited over the interconnect, and an electrically conductive layer is electrolytically deposited over the seed layer substantially filling the channels and vias. The interconnect surface is then planarized by polishing until the electrical conductor remains only in the channels and vias.

摘要翻译： 可以在相对较少的步骤中以低成本的蚀刻和图案化技术形成通过部分延伸的通孔和完全延伸穿过例如基板或集成电路的电互连中的绝缘层的通孔。 然后可以以相对较少的步骤在通道和通孔中填充电导体。 在一个实施例中，将通孔和通道暴露的不可侵蚀的硬掩模放置在聚酰亚胺层上，暴露通孔但覆盖通道的可侵蚀的软掩模置于硬掩模上，并施加等离子体蚀刻。 蚀刻通孔区域直到软掩模完全侵蚀，然后蚀刻通孔区和通道区，以提供部分蚀刻的通道和完全蚀刻的通孔。 此后，种子层沉积在互连上，并且导电层电解沉积在种子层上，基本上填充通道和通孔。 然后通过抛光将互连表面平坦化，直到电导体仅保留在通道和通孔中。

公开(公告)号：US5034347A

公开(公告)日：1991-07-23

申请号：US575242

申请日：1990-08-30

申请人： Sanehiko Kakihana

发明人： Sanehiko Kakihana

IPC分类号： H01L21/74 ,  H01L23/48

CPC分类号： H01L21/743 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10S438/945

摘要： Disclosed is a process for producing a monolithic microwave integrated circuit device utilizing a body having a first thickness in the heat producing region and a second thickness in the region adjacent to the microstrip transmission lines.

摘要翻译： 公开了一种利用在发热区域中具有第一厚度的主体和在与微带传输线相邻的区域中的第二厚度的单片微波集成电路器件的制造方法。