公开(公告)号：US11803328B2

公开(公告)日：2023-10-31

申请号：US17428105

申请日：2020-02-05

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G06F3/06 ,  G06F13/16 ,  G06F13/42

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0673 ,  G06F13/1668 ,  G06F13/4282

Abstract: An integrated-circuit memory component receives, as part of respective first and second memory read transactions, a first column access command that identifies a first volume of data and a second column read command that identifies a second volume of data, the second volume of data being constituted by not more than half as many data bits as the first volume of data. In response to receiving the first column access command, the integrated-circuit memory component transmits the first volume of data as N parallel bit-serial data signals over N external signaling links. In response to receiving the second column access command, the integrated-circuit memory component transmits the second volume of data as M parallel bit-serial data signals over M of the N external signaling links, where M is less than N.

公开(公告)号：US11803323B2

公开(公告)日：2023-10-31

申请号：US17608426

申请日：2020-04-28

Applicant: RAMBUS INC.

Inventor： Christopher Haywood ,  Frederick A. Ware

IPC: G06F3/06

CPC classification number: G06F3/0656 ,  G06F3/061 ,  G06F3/0673

Abstract: A cascaded memory system includes a memory module having a primary interface coupled to a memory controller via a first communication channel and a secondary interface coupled to a second memory module via a second communication channel. The first memory module buffers and repeats signals received on the primary and secondary interfaces to enable communications between the memory controller and the secondary memory module.

公开(公告)号：US11797227B2

公开(公告)日：2023-10-24

申请号：US16405479

申请日：2019-05-07

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Craig E. Hampel ,  Wayne S. Richardson ,  Chad A. Bellows ,  Lawrence Lai

IPC: G06F3/06 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4097 ,  G11C8/06

CPC classification number: G06F3/0659 ,  G06F3/0613 ,  G06F3/0673 ,  G11C7/1006 ,  G11C7/1042 ,  G11C7/22 ,  G11C8/06 ,  G11C11/4076 ,  G11C11/4097

Abstract: A micro-threaded memory device. A plurality of storage banks are provided, each including a plurality of rows of storage cells and having an access restriction in that at least a minimum access time interval must transpire between successive accesses to a given row of the storage cells. Transfer control circuitry is provided to transfer a first amount of data between the plurality of storage banks and an external signal path in response to a first memory access request, the first amount of data being less than a product of the external signal path bandwidth and the minimum access time interval.

公开(公告)号：US11790973B2

公开(公告)日：2023-10-17

申请号：US17376032

申请日：2021-07-14

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Brent Steven Haukness ,  Kenneth L. Wright ,  Thomas Vogelsang

IPC: G11C11/34 ,  G11C11/403 ,  G11C11/4097 ,  G11C11/4096 ,  G11C8/08 ,  G11C7/10 ,  G11C7/18 ,  G11C5/02 ,  G11C11/408 ,  G06F12/06 ,  G11C11/406 ,  G11C11/409 ,  G11C11/4091

CPC classification number: G11C11/403 ,  G06F12/06 ,  G11C5/025 ,  G11C7/1018 ,  G11C7/1045 ,  G11C7/1096 ,  G11C7/18 ,  G11C8/08 ,  G11C11/408 ,  G11C11/409 ,  G11C11/4085 ,  G11C11/4096 ,  G11C11/4097 ,  G11C11/40618 ,  G11C11/4091

Abstract: A memory component includes a first memory bank. The first memory bank has a plurality of sub-arrays having sub-rows of memory elements. The memory component includes a write driver, coupled to the first memory bank, to perform a write operation of an entire sub-row of a sub-array. To perform the write operation, the write driver is to load a burst of write data to the memory bank. The memory bank may then activate a plurality of sense amplifiers associated with a plurality of memory elements of the entire sub-row to load the burst of write data to the plurality of sense amplifiers.

公开(公告)号：US20230307079A1

公开(公告)日：2023-09-28

申请号：US18295445

申请日：2023-04-04

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt

IPC: G11C29/42 ,  G11C29/12 ,  G11C29/18 ,  G11C29/44 ,  G06F11/10

CPC classification number: G11C29/42 ,  G11C29/1201 ,  G11C29/18 ,  G11C29/4401 ,  G06F11/1012 ,  G06F11/1016 ,  G06F11/1032 ,  G06F11/1048

Abstract: A memory controller generates error codes associates with write data and a write address and provides the error codes over a dedicated error detection code link to a memory device during a write operation. The memory device performs error detection, and in some cases correction, on the received write data and write address based on the error codes. If no uncorrectable errors are detected, the memory device furthermore stores the error codes in association with the write data. On a read operation, the memory device outputs the error codes over the error detection code link to the memory controller together with the read data. The memory controller performs error detection, and in some cases correction, on the received read data based on the error codes.

公开(公告)号：US20230307026A1

公开(公告)日：2023-09-28

申请号：US18094908

申请日：2023-01-09

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely Tsern ,  John Eric Linstadt

IPC: G11C11/00 ,  G11C5/04 ,  G11C5/06 ,  G06F3/06 ,  G06F11/10 ,  G11C7/10 ,  G11C7/12

CPC classification number: G11C11/005 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0673 ,  G06F11/1004 ,  G06F11/1076 ,  G11C5/04 ,  G11C5/063 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/12

Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory module includes a pin interface for coupling to a memory controller via a bus. The module includes at least two non-volatile memory devices, and a buffer disposed between the pin interface and the at least two non-volatile memory devices. The buffer receives non-volatile memory access commands from the memory controller that are interleaved with DRAM memory module access commands.

公开(公告)号：US20230244293A1

公开(公告)日：2023-08-03

申请号：US18092004

申请日：2022-12-30

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Robert E. Palmer ,  John W. Poulton ,  Andrew M. Fuller

IPC: G06F1/3237 ,  G11C7/04 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  G06F13/16 ,  G06F1/12 ,  G06F1/3225 ,  G06F1/324 ,  G06F3/06

CPC classification number: G06F1/3237 ,  G11C7/04 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/222 ,  G11C7/225 ,  G11C11/4076 ,  G11C11/4096 ,  G06F13/1689 ,  G11C7/22 ,  G06F1/12 ,  G06F1/3225 ,  G06F1/324 ,  G06F3/0604 ,  G06F3/0625 ,  G06F3/0629 ,  G06F3/0673 ,  G06F9/3836

Abstract: A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more timing signals required to time data signaling operations within synchronous communication circuits of one or more attached memory devices and also disables one or more power consuming circuits within the synchronous communication circuits of the one or more memory devices.

公开(公告)号：US20230238041A1

公开(公告)日：2023-07-27

申请号：US18089668

申请日：2022-12-28

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  Frederick A. Ware ,  William N. Ng

IPC: G11C7/10 ,  G11C5/04

CPC classification number: G11C7/1093 ,  G11C5/04 ,  G11C7/1003 ,  G11C7/1066

Abstract: A memory module can be programmed to deliver relatively wide, low-latency data in a first access mode, or to sacrifice some latency in return for a narrower data width, a narrower command width, or both, in a second access mode. The narrow, higher-latency mode requires fewer connections and traces. A controller can therefore support more modules, and thus increased system capacity. Programmable modules thus allow computer manufacturers to strike a desired balance between memory latency, capacity, and cost.

公开(公告)号：US11664907B2

公开(公告)日：2023-05-30

申请号：US17575255

申请日：2022-01-13

Applicant: Rambus Inc.

Inventor： Craig E. Hampel ,  Frederick A. Ware ,  Richard E. Perego

IPC: H04B17/11 ,  H04L7/10 ,  H04L7/00 ,  H04L7/04 ,  H04L27/00 ,  H04B17/21 ,  H04B17/00

CPC classification number: H04B17/11 ,  H04B17/00 ,  H04B17/21 ,  H04L7/0004 ,  H04L7/0016 ,  H04L7/0087 ,  H04L7/043 ,  H04L7/10 ,  H04L27/00

Abstract: A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameter, and to update the operation value in response to the measured drift. The second calibration sequence utilizes less resources of the communication channel than does the first calibration sequence. In one embodiment, the first calibration sequence for measurement and convergence on the operation value utilizes long calibration patterns, such as codes that are greater than 30 bytes, or pseudorandom bit sequences having lengths of 2N−1 bits, where N is equal to or greater than 7, while the second calibration sequence utilizes short calibration patterns, such as fixed codes less than 16 bytes, and for example as short as 2 bytes long.

公开(公告)号：US11657006B2

公开(公告)日：2023-05-23

申请号：US17461064

申请日：2021-08-30

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G06F13/16

CPC classification number: G06F13/1615 ,  G06F13/1689

Abstract: A memory device includes receivers that use CMOS signaling levels (or other relatively large signal swing levels) on its command/address and data interfaces. The memory device also includes an asynchronous timing input that causes the reception of command and address information from the CMOS level receivers to be decoded and forwarded to the memory core (which is self-timed) without the need for a clock signal on the memory device's primary clock input. Thus, an activate row command can be received and initiated by the memory core before the memory device has finished exiting the low power state. Because the row operation is begun before the exit wait time has elapsed, the latency of one or more accesses (or other operations) following the exit from the low power state is reduced.