POWER OVER DATA LINES SYSTEM WITH REDUNDANT POWER CONNECTIONS

    公开(公告)号:US20170310491A1

    公开(公告)日:2017-10-26

    申请号:US15479187

    申请日:2017-04-04

    Abstract: In one embodiment, a master device has a first port and a second port and initially applies a DC voltage only to the first port. A plurality of slave devices, each have a third port and a fourth port, are serially connected to the master device in a ring, via conductors, starting at the first port and ending at the second port. The conductors simultaneously carry the DC voltage and differential data. Each slave device, after performing a detection routine, then sequentially applies the DC voltage to the adjacent downstream slave device in a first direction around the ring. If the master does not detect the presence of the DC voltage at its second port, the master device applies the DC voltage to both the first port and the second port to sequentially power up the slave devices in both directions around the ring of slave devices.

    MULTIPHASE SWITCHING POWER SUPPLY WITH ROBUST CURRENT SENSING AND SHARED AMPLIFIER

    公开(公告)号:US20170302174A1

    公开(公告)日:2017-10-19

    申请号:US15479162

    申请日:2017-04-04

    Abstract: In a multiphase, current mode controlled switching power supply, current through the inductors in the various phases is sensed to determine when to turn off the switching transistors. An AC current feedback path, sensing the ramping ripple current, is separate from the DC current path, sensing the lower frequency average current. A shared differential amplifier has its inputs multiplexed to receive only the DC component signals from all the phases. The gain of the amplifier is set so that the DC sense signal has the proper proportion to the AC sense signal. The output of the amplifier is sampled and held for each phase using a second multiplexer. The AC sense signal and the amplified DC sense signal, for each phase, are combined by a summing circuit. The composite sense signal is applied to a comparator for each phase to control the duty cycle of the associated switch.

    Multiphase switching power supply with robust current sensing and shared amplifier

    公开(公告)号:US09793800B1

    公开(公告)日:2017-10-17

    申请号:US15479162

    申请日:2017-04-04

    Abstract: In a multiphase, current mode controlled switching power supply, current through the inductors in the various phases is sensed to determine when to turn off the switching transistors. An AC current feedback path, sensing the ramping ripple current, is separate from the DC current path, sensing the lower frequency average current. A shared differential amplifier has its inputs multiplexed to receive only the DC component signals from all the phases. The gain of the amplifier is set so that the DC sense signal has the proper proportion to the AC sense signal. The output of the amplifier is sampled and held for each phase using a second multiplexer. The AC sense signal and the amplified DC sense signal, for each phase, are combined by a summing circuit. The composite sense signal is applied to a comparator for each phase to control the duty cycle of the associated switch.

    DCR inductor current-sensing in four-switch buck-boost converters

    公开(公告)号:US09748843B2

    公开(公告)日:2017-08-29

    申请号:US14677794

    申请日:2015-04-02

    CPC classification number: H02M3/1582 H02M2001/0009

    Abstract: An inductor current-sensing circuit for measuring a current in an inductor includes (a) a first RC network coupled between a first terminal of the inductor and a reference voltage source; and (b) a second RC network coupled between a second terminal of the inductor and the reference voltage source. The first RC network and the second RC network each have a time constant substantially equal to the ratio between the inductance and the DC resistance of the inductor. The inductor which current is being measured may be a primary inductor of a four-switch buck boost converter receiving an input voltage and providing an output voltage.

    Notch filter for ripple reduction
    76.
    发明授权

    公开(公告)号:US09685933B2

    公开(公告)日:2017-06-20

    申请号:US14669863

    申请日:2015-03-26

    CPC classification number: H03H19/004 H02M1/15 H02M3/07 H03F3/45475

    Abstract: A notch filter is controlled synchronously with a chopper to filter out chopping ripple. In one embodiment, the notch filter is coupled to the differential output of the chopper and includes a sampling capacitor, a hold capacitor, and a second set of switches between the sampling capacitor and the hold capacitor. The second set of switches is temporarily closed once per chopper switching cycle to transfer charge from the sampling capacitor to the hold capacitor such that the ripple from the chopper is not transferred to the hold capacitor. The voltage across the hold capacitor may be coupled to any other circuit, such as to the differential inputs of an amplifier.

    SYSTEM AND METHOD FOR SYNCHRONIZATION AMONG MULTIPLE PLL-BASED CLOCK SIGNALS

    公开(公告)号:US20170134031A1

    公开(公告)日:2017-05-11

    申请号:US15208482

    申请日:2016-07-12

    CPC classification number: G06F1/12 G06F1/10 H03L7/23

    Abstract: A method synchronizes clock signals generated by a system that includes multiple PLLs that are connected in parallel and output frequency dividers driven by the PLLs. The system receives a common frequency reference signal and a common synchronization signal. Each PLL may have a reference signal frequency divider. The reference frequency divider may be phase-reset, for example, by a transition to a first logic state in the synchronization signal, and the output frequency dividers are each phase-reset, for example, by a transition to a second logic state following the transition to the first logic state in the synchronization signal. The transition to the first logic state may be, for example, a rising edge.

    Detection scheme for four wire pair Power Over Ethernet system

    公开(公告)号:US09634844B2

    公开(公告)日:2017-04-25

    申请号:US14607608

    申请日:2015-01-28

    CPC classification number: H04L12/10 G06F1/26

    Abstract: In a method performed by a PoE system, a PSE is able to detect whether a PD is compatible for receiving power via four wire pairs in the standard Ethernet cable. The PSE provides a current limited voltage to a first and second pair of wires in the cable, during a detection phase, to detect a characteristic impedance of the PD. In the PSE, a first resistor is connected to a third wire pair and a second resistor is connected to a fourth wire pair. During the detection phase, the PSE detects the relative currents through the resistors. If the currents are the same, then the PSE knows the PD is able to receive power via the four wire pairs. The PSE then applies the full PoE voltage to the first and second wire pairs and connects the third and fourth wire pairs to a low voltage via a MOSFET.

    MOSFET protection using resistor-capacitor thermal network

    公开(公告)号:US09634480B1

    公开(公告)日:2017-04-25

    申请号:US14486697

    申请日:2014-09-15

    Abstract: A circuit for protecting a semiconductor element is provided in a system for supplying power from an input node to an output node. The circuit has an analog multiplier responsive to a voltage across the semiconductor element and a current flowing through the semiconductor element to produce an output voltage. A transconductance amplifier is coupled to an output of the analog multiplier for receiving the output voltage of the analog multiplier to produce an output current. An analog RC circuit coupled to the output of the transconductance amplifier is configurable to include a selected number of resistive elements having selected resistance values and a selected number of capacitive elements having selected capacitance values. The configuration of the RC circuit is carried out to provide an RC thermal model that reproduces a desired thermal behavior of the semiconductor element. The RC circuit is responsive to the output current of the transconductance amplifier to produce an output voltage used to control the semiconductor element.

    Maintaining output capacitance voltage in LED driver systems during PWM off times
    80.
    发明授权
    Maintaining output capacitance voltage in LED driver systems during PWM off times 有权
    在PWM关闭时间期间维持LED驱动器系统中的输出电容电压

    公开(公告)号:US09596728B2

    公开(公告)日:2017-03-14

    申请号:US15147842

    申请日:2016-05-05

    Abstract: A method and system of driving an LED load. A driver is configured to deliver a level of current indicated by a control signal to the LED load when a PWM signal is ON and stop delivering the level of current when the PWM signal is OFF. An output capacitance element is coupled across a differential output of the LED driver. A feedback path, having a store circuit, is configured to store an information indicative of a first voltage level across the output capacitance element as a stored feedback reference signal just after the PWM signal is turned OFF. The feedback path causes the voltage across the output capacitance element to be at the first voltage level just before the PWM signal is turned ON.

    Abstract translation: 驱动LED负载的方法和系统。 驱动器被配置为当PWM信号为ON时将控制信号指示的电流电平传递给LED负载,并且当PWM信号为OFF时停止传送电流电平。 输出电容元件跨越LED驱动器的差分输出耦合。 具有存储电路的反馈路径被配置为在PWM信号关闭之后存储指示输出电容元件上的第一电压电平的信息作为存储的反馈参考信号。 反馈路径使得输出电容元件两端的电压在PWM信号接通之前处于第一电压电平。

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