公开(公告)号：US09959927B2

公开(公告)日：2018-05-01

申请号：US15404087

申请日：2017-01-11

Applicant: Silicon Storage Technology, Inc. ,  Agency For Science, Technology And Research

Inventor： Feng Zhou ,  Xian Liu ,  Nhan Do ,  Hieu Van Tran ,  Hung Quoc Nguyen ,  Mark Reiten ,  Zhixian Chen ,  Wang Xinpeng ,  Guo-Qiang Lo

IPC: G11C16/04 ,  G11C13/00 ,  H01L45/00

CPC classification number: G11C13/0007 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16

Abstract: A memory device and method comprising a metal oxide material disposed between and in electrical contact with first and second conductive electrodes, and a voltage source configured to apply a plurality of voltage pulses spaced apart in time across the first and second electrodes. For each one of the voltage pulses, an amplitude of the voltage increases during the voltage pulse.

公开(公告)号：US20180075914A1

公开(公告)日：2018-03-15

申请号：US15690159

申请日：2017-08-29

Applicant: Silicon Storage Technology, Inc.

Inventor： Bin Sheng ,  Yao Zhou ,  Tao Wang ,  Xiaozhou Qian ,  Lu Guo ,  Ning Bai

IPC: G11C16/28

CPC classification number: G11C16/28 ,  G11C16/0425 ,  G11C16/08

Abstract: The present invention relates to an improved sense amplifier for reading values in flash memory cells in an array. In one embodiment, a sense amplifier comprises an improved pre-charge circuit for pre-charging a bit line during a pre-charge period to increase the speed of read operations. In another embodiment, a sense amplifier comprises simplified address decoding circuitry to increase the speed of read operations.

公开(公告)号：US09910473B2

公开(公告)日：2018-03-06

申请号：US13830246

申请日：2013-03-14

Applicant: Silicon Storage Technology, Inc.

Inventor： Hung Quoc Nguyen ,  Hieu Van Tran ,  Hung Thanh Nguyen

IPC: G06F1/32 ,  G06F1/16 ,  G11C5/14 ,  G11C7/08 ,  G11C7/10 ,  G11C7/20 ,  G11C7/22

CPC classification number: G06F1/32 ,  G11C5/14 ,  G11C7/08 ,  G11C7/1072 ,  G11C7/20 ,  G11C7/222 ,  G11C2207/065 ,  G11C2207/2227

Abstract: An improved method and apparatus for performing power management in a memory device is disclosed.

公开(公告)号：US20180033482A1

公开(公告)日：2018-02-01

申请号：US15597709

申请日：2017-05-17

Applicant: Silicon Storage Technology, Inc. ,  Agency For Science, Technology, and Research

Inventor： Santosh Hariharan ,  Hieu Van Tran ,  Feng Zhou ,  Xian Liu ,  Steven Lemke ,  Nhan Do ,  Zhixian Chen ,  Xinpeng Wang

IPC: G11C13/00 ,  H01L27/24 ,  H01L45/00

CPC classification number: G11C13/0011 ,  G11C11/00 ,  G11C13/0007 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0066 ,  G11C2013/0078 ,  G11C2013/0083 ,  G11C2013/0088 ,  G11C2013/0092 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/085 ,  H01L45/146

Abstract: A memory device includes a metal oxide material disposed between and in electrical contact with first and second conductive electrodes, and an electrical current source configured to apply one or more electrical current pulses through the metal oxide material. For each of the one or more electrical current pulses, an amplitude of the electrical current increases over time during the electrical current pulse to form a conductive filament in metal oxide material.

公开(公告)号：US09882033B2

公开(公告)日：2018-01-30

申请号：US15368451

申请日：2016-12-02

Applicant: Silicon Storage Technology, Inc.

Inventor： Nhan Do

IPC: G11C11/34 ,  H01L29/792 ,  H01L21/3205 ,  H01L29/788 ,  H01L29/66 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/423 ,  H01L21/02

CPC classification number: H01L29/66833 ,  H01L21/0217 ,  H01L27/1052 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/42352 ,  H01L29/66825 ,  H01L29/7926

Abstract: A memory cell formed by forming a trench in the surface of a substrate. First and second spaced apart regions are formed in the substrate with a channel region therebetween. The first region is formed under the trench. The channel region includes a first portion that extends along a sidewall of the trench and a second portion that extends along the surface of the substrate. A charge trapping layer in the trench is adjacent to and insulated from the first portion of the channel region for controlling the conduction of the channel region first portion. An electrically conductive gate in the trench is adjacent to and insulated from the charge trapping layer and from the first region and is capacitively coupled to the charge trapping layer. An electrically conductive control gate is disposed over and insulated from the second portion of the channel region for controlling its conduction.

公开(公告)号：US20170373077A1

公开(公告)日：2017-12-28

申请号：US15701357

申请日：2017-09-11

Applicant: Silicon Storage Technology, Inc.

Inventor： Chien-Sheng Su ,  Jeng-Wei Yang ,  Feng Zhou

IPC: H01L27/11531 ,  H01L27/11524 ,  H01L27/11521 ,  H01L29/423 ,  H01L29/788 ,  H01L29/66

CPC classification number: H01L27/11531 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42328 ,  H01L29/66484 ,  H01L29/66825 ,  H01L29/7881

Abstract: A method of forming split gate non-volatile memory cells on the same chip as logic and high voltage devices having HKMG logic gates. The method includes forming the source and drain regions, floating gates, control gates, and the poly layer for the erase gates and word line gates in the memory area of the chip. A protective insulation layer is formed over the memory area, and an HKMG layer and poly layer are formed on the chip, removed from the memory area, and patterned in the logic areas of the chip to form the logic gates having varying amounts of underlying insulation.

公开(公告)号：US20170337971A1

公开(公告)日：2017-11-23

申请号：US15593231

申请日：2017-05-11

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Vipin Tiwari ,  Nhan Do

IPC: G11C16/14

CPC classification number: G11C16/14 ,  G11C16/0425 ,  G11C16/10

Abstract: A memory device and method of erasing same that includes a substrate of semiconductor material and a plurality of memory cells formed on the substrate and arranged in an array of rows and columns. Each of the memory cells includes spaced apart source and drain regions in the substrate, with a channel region in the substrate extending there between, a floating gate disposed over and insulated from a first portion of the channel region which is adjacent the source region, a select gate disposed over and insulated from a second portion of the channel region which is adjacent the drain region, and a program-erase gate disposed over and insulated from the source region. The program-erase gate lines alone or in combination with the select gate lines, or the source lines, are arranged in the column direction so that each memory cell can be individually programmed, read and erased.

公开(公告)号：US09793280B2

公开(公告)日：2017-10-17

申请号：US15057590

申请日：2016-03-01

Applicant: Silicon Storage Technology, Inc.

Inventor： Chun-Ming Chen ,  Jeng-Wei Yang ,  Chien-Sheng Su ,  Man-Tang Wu ,  Nhan Do

IPC: H01L29/66 ,  H01L27/11531 ,  H01L29/423 ,  H01L21/28 ,  H01L27/11534 ,  G11C16/04

CPC classification number: H01L27/11531 ,  G11C16/0425 ,  H01L21/28273 ,  H01L27/11534 ,  H01L29/42328 ,  H01L29/66825

Abstract: A memory device and method including a semiconductor substrate with memory and logic device areas. A plurality of memory cells are formed in the memory area, each including first source and drain regions with a first channel region therebetween, a floating gate disposed over a first portion of the first channel region, a control gate disposed over the floating gate, a select gate disposed over a second portion of the first channel region, and an erase gate disposed over the source region. A plurality of logic devices formed in the logic device area, each including second source and drain regions with a second channel region therebetween, and a logic gate disposed over the second channel region. The substrate upper surface is recessed lower in the memory area than in the logic device area, so that the taller memory cells have an upper height similar to that of the logic devices.

公开(公告)号：US20170194055A1

公开(公告)日：2017-07-06

申请号：US15371496

申请日：2016-12-07

Applicant: Silicon Storage Technology, Inc.

Inventor： Xiaozhou Qian ,  Xiao Yan Pi ,  Kai Man Yue ,  Qing Rao ,  Lisa Bian

IPC: G11C16/26 ,  G11C16/24

CPC classification number: G11C16/26 ,  G11C7/062 ,  G11C7/067 ,  G11C7/14 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/28 ,  G11C16/32 ,  G11C2207/2254

Abstract: Multiple embodiments of a low power sense amplifier for use in a flash memory system are disclosed. In some embodiments, the loading on a sense amplifier can be adjusted by selectively attaching one or more bit lines to the sense amplifier, where the one or more bit lines each is coupled to an extraneous memory cell.

公开(公告)号：US20170179141A1

公开(公告)日：2017-06-22

申请号：US15453829

申请日：2017-03-08

Applicant: Silicon Storage Technology, Inc.

Inventor： Chien-Sheng Su ,  Jeng-Wei Yang ,  Man-Tang Wu ,  Chun-Ming Chen ,  Hieu Van Tran ,  Nhan Do

IPC: H01L27/11521 ,  H01L29/788 ,  H01L29/08 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/1052 ,  H01L27/11551 ,  H01L29/0847 ,  H01L29/42328 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/66825 ,  H01L29/785 ,  H01L29/7856 ,  H01L29/7881

Abstract: A non-volatile memory cell, and method of making, that includes a semiconductor substrate having a fin shaped upper surface with a top surface and two side surfaces. Source and drain regions are formed in the fin shaped upper surface portion with a channel region there between. A conductive floating gate includes a first portion extending along a first portion of the top surface, and second and third portions extending along first portions of the two side surfaces, respectively. A conductive control gate includes a first portion extending along a second portion of the top surface, second and third portions extending along second portions of the two side surfaces respectively, a fourth portion extending up and over at least some of the floating gate first portion, and fifth and sixth portions extending out and over at least some of the floating gate second and third portions respectively.