公开(公告)号：US20130335928A1

公开(公告)日：2013-12-19

申请号：US13780421

申请日：2013-02-28

Applicant: UNIMICRON TECHNOLOGY CORPORATION

Inventor： Tzyy-Jang Tseng ,  Chung W. Ho ,  Dyi-Chung Hu ,  Huan-Ling Lee ,  Sheng-Yuah He

IPC: H05K3/10 ,  H05K1/02

CPC classification number: H05K1/05 ,  H01L21/568 ,  H01L23/145 ,  H01L23/49811 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K1/02 ,  H05K1/0271 ,  H05K3/10 ,  H05K3/4644 ,  H05K3/4682 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A fabrication method of a coreless packaging substrate is provided, including the steps of: forming an inner built-up circuit board on a carrier; removing the carrier; and symmetrically forming a first outer built-up structure and a second outer built-up structure on top and bottom surfaces of the inner built-up circuit board, respectively. The present invention effectively increases the product yield, saves the fabrication cost, and reduces wastes.

Abstract translation: 提供一种无芯封装基板的制造方法，包括以下步骤：在载体上形成内层叠电路板; 移除载体; 并且分别在内部堆叠电路板的顶表面和底表面上对称地形成第一外部组合结构和第二外部组合结构。 本发明有效地提高了产品产量，节省了制造成本，并且减少了废物。

公开(公告)号：US20130309817A1

公开(公告)日：2013-11-21

申请号：US13948671

申请日：2013-07-23

Applicant: UNIMICRON TECHNOLOGY CORPORATION

Inventor： Tzyy-Jang Tseng ,  Dyi-Chung Hu ,  Yu-Shan Hu

IPC: H01L21/56

CPC classification number: H01L21/56 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/4334 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/20 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/214 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/4824 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00013 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2224/29099 ,  H01L2224/83 ,  H01L2224/19 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29599 ,  H01L2924/00

Abstract: A package structure includes a metal sheet having perforations; a semiconductor chip having an active surface and an opposite inactive surface, wherein the active surface has electrode pads thereon, conductive bumps are disposed on the electrode pads, the semiconductor chip is combined with the metal sheet via the inactive surface thereof, a protective buffer layer is formed on the active surface to cover the conductive bumps, and the perforations are arranged around a periphery of the inactive surface of the semiconductor chip; an encapsulant formed on the metal sheet and in the perforations, for encapsulating the semiconductor chip and exposing the protective buffer layer; and a circuit fan-out layer formed on the encapsulant and the protective buffer layer and having conductive vias penetrating the protective buffer layer and electrically connecting to the conductive bumps. A method of fabricating the package structure and a package-on-package device including the package structure are also provided.

Abstract translation: 包装结构包括具有穿孔的金属片; 具有活性表面和相反的非活性表面的半导体芯片，其中活性表面上具有电极焊盘，导电凸块设置在电极焊盘上，半导体芯片通过其非活性表面与金属片组合，保护缓冲层 形成在活性表面上以覆盖导电凸块，并且穿孔布置在半导体芯片的非活性表面周围; 形成在所述金属片上和所述穿孔中的密封剂，用于封装所述半导体芯片并暴露所述保护缓冲层; 以及形成在密封剂和保护缓冲层上并具有穿过保护缓冲层并且电连接到导电凸块的导电通孔的电路扇出层。 还提供了制造封装结构的方法和包括封装结构的封装封装器件。

公开(公告)号：US20130249083A1

公开(公告)日：2013-09-26

申请号：US13753906

申请日：2013-01-30

Applicant: UNIMICRON TECHNOLOGY CORPORATION

Inventor： Dyi-Chung Hu ,  Ying-Chih Chan ,  Chun-Ting Lin

IPC: H01L23/498

CPC classification number: H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A packaging substrate is provided, wherein a plurality of conductive posts together with a conductive bonding layer formed thereon form a plurality of external connection structures with the same height, thereby preventing tilted stack structures and poor coplanarity in a subsequent stacking process.

Abstract translation: 提供了一种封装基板，其中多个导电柱与其上形成的导电接合层一起形成具有相同高度的多个外部连接结构，从而防止在随后的堆叠过程中倾斜的堆叠结构和差的共面性。

公开(公告)号：US20130118680A1

公开(公告)日：2013-05-16

申请号：US13738526

申请日：2013-01-10

Applicant: UNIMICRON TECHNOLOGY CORPORATION

Inventor： Chin-Ming Liu

IPC: H05K13/00

CPC classification number: H05K13/00 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K3/0097 ,  H05K3/4682 ,  H05K2203/0152 ,  H05K2203/1536 ,  Y10T156/10 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A method for fabricating a packaging substrate includes: stacking two metal layers;encapsulating the two metal layers with assistant dielectric layers; forming built-up structures on the assistant dielectric layers, respectively; and separating the built-up structures along the interface between the two metal layers so as to form two packaging substrates. Owing to the adhesive characteristic of the assistant dielectric layers, the two metal layers are unlikely to separate from each other during formation of the built-up structures. But after portions of the dielectric layer around the periphery of the metal layers are cut and removed, the two metal layers can be readily separated from each other. The two metal layers can be patterned to form wiring layers, metal bumps, or supporting structures to avoid waste of materials. A packaging substrate and a fabrication method thereof are provided.

Abstract translation: 一种用于制造封装衬底的方法包括：堆叠两个金属层; 用辅助电介质层封装两个金属层; 分别在辅助电介质层上形成堆积结构; 并且沿着两个金属层之间的界面分离堆积结构，以形成两个封装基板。 由于辅助电介质层的粘合特性，在形成构造结构期间，两个金属层不可能彼此分离。 但是，在金属层周围的电介质层的部分被切割和去除之后，两个金属层可以容易地彼此分离。 可以将两个金属层图案化以形成布线层，金属凸块或支撑结构，以避免材料浪费。 提供了一种封装基板及其制造方法。

公开(公告)号：US20130062100A1

公开(公告)日：2013-03-14

申请号：US13667651

申请日：2012-11-02

Applicant: Unimicron Technology Corporation

Inventor： Kun-Chen Tsai

IPC: H05K1/11 ,  H05K1/09

CPC classification number: H05K3/205 ,  H01L2924/0002 ,  H05K3/423 ,  H05K3/465 ,  H05K3/4682 ,  H05K2201/09563 ,  H05K2201/09881 ,  Y10T29/49128 ,  Y10T29/49165 ,  H01L2924/00

Abstract: Provided are a circuit board structure and a fabrication method thereof, including the steps of: forming a first circuit layer in a first dielectric layer and exposing the first circuit layer therefrom; forming a second dielectric layer on the first dielectric layer and the first circuit layer, and forming a second circuit layer on the second dielectric layer; forming a plurality of first conductive vias in the second dielectric layer for electrically connecting to the first circuit layer to thereby dispense with a core board and electroplated holes and thus facilitate miniaturization. Further, the first dielectric layer is liquid before being hardened and is formed on the first dielectric layer that enhances the bonding between layers of the circuit board and the structure.

Abstract translation: 提供一种电路板结构及其制造方法，包括以下步骤：在第一电介质层中形成第一电路层，并从其露出第一电路层; 在所述第一电介质层和所述第一电路层上形成第二电介质层，以及在所述第二电介质层上形成第二电路层; 在第二电介质层中形成多个第一导电通孔，用于电连接到第一电路层，从而省去芯板和电镀孔，从而便于小型化。 此外，第一电介质层在硬化之前是液体，并且形成在增强电路板的层之间的结合的第一电介质层和结构之间。