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158 条记录 (耗时 0.036 秒)

    Intralevel conductive light shield
    72.
    发明授权
    Intralevel conductive light shield 有权
    Intralevel导电灯罩

    公开(公告)号：US08709855B2

    公开(公告)日：2014-04-29

    申请号：US12133379

    申请日：2008-06-05

    申请人： Jeffrey P. Gambino ,  Zhong-Xiang He ,  Kevin N. Ogg ,  Richard J. Rassel ,  Robert M. Rassel

    发明人： Jeffrey P. Gambino ,  Zhong-Xiang He ,  Kevin N. Ogg ,  Richard J. Rassel ,  Robert M. Rassel

    IPC分类号： H01L21/00

    CPC分类号： H01L23/552 ,  H01L27/14623 ,  H01L27/14636 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A conductive light shield is formed over a first dielectric layer of a via level in a metal interconnect structure. The conductive light shield is covers a floating drain of an image sensor pixel cell. A second dielectric layer is formed over the conductive light shield and at least one via extending from a top surface of the second dielectric layer to a bottom surface of the first dielectric layer is formed in the metal interconnect structure. The conductive light shield may be formed within a contact level between a top surface of a semiconductor substrate and a first metal line level, or may be formed in any metal interconnect via level between two metal line levels. The inventive image sensor pixel cell is less prone to noise due to the blockage of light over the floating drain by the conductive light shield.

    摘要翻译： 在金属互连结构中的通孔级的第一介电层上形成导电屏蔽。 导电屏蔽覆盖图像传感器像素单元的浮动漏极。 在导电光屏蔽上形成第二电介质层，并且在金属互连结构中形成有从第二电介质层的顶表面延伸到第一介电层的底表面的至少一个通孔。 导电屏蔽可以形成在半导体衬底的顶表面和第一金属线电平之间的接触电平内，或者可以通过两个金属线电平之间的电平形成在任何金属互连中。 本发明的图像传感器像素单元由于在导电屏蔽层上的浮动漏极上的光阻塞而不容易产生噪声。

    Semiconductor structure including trench capacitor and trench resistor
    75.
    发明授权
    Semiconductor structure including trench capacitor and trench resistor 有权
    半导体结构包括沟槽电容和沟槽电阻

    公开(公告)号：US08110862B2

    公开(公告)日：2012-02-07

    申请号：US12499452

    申请日：2009-07-08

    申请人： Kangguo Cheng ,  Robert M. Rassel

    发明人： Kangguo Cheng ,  Robert M. Rassel

    IPC分类号： H01L29/94 ,  H01L21/283

    CPC分类号： H01L29/945 ,  H01L27/016 ,  H01L27/0682 ,  H01L28/20 ,  H01L29/66181

    摘要： A structure and a method for fabrication of the structure use a capacitor trench for a trench capacitor and a resistor trench for a trench resistor. The structure is typically a semiconductor structure. In a first instance, the capacitor trench has a linewidth dimension narrower than the resistor trench. The trench linewidth difference provides an efficient method for fabricating the trench capacitor and the trench resistor. In a second instance, the trench resistor comprises a conductor material at a periphery of the resistor trench and a resistor material at a central portion of the resistor trench.

    摘要翻译： 用于制造结构的结构和方法使用用于沟槽电容器的电容器沟槽和用于沟槽电阻器的电阻器沟槽。 该结构通常是半导体结构。 在第一种情况下，电容器沟槽的线宽尺寸比电阻器沟槽窄。 沟槽线宽差提供了制造沟槽电容器和沟槽电阻器的有效方法。 在第二种情况下，沟槽电阻器包括在电阻器沟槽的周边处的导体材料和在电阻器沟槽的中心部分处的电阻器材料。

    SCHOTTKY BARRIER DIODE WITH PERIMETER CAPACITANCE WELL JUNCTION
    76.
    发明申请
    SCHOTTKY BARRIER DIODE WITH PERIMETER CAPACITANCE WELL JUNCTION 有权
    肖特基二极管与周边电容良好连接

    公开(公告)号：US20120018837A1

    公开(公告)日：2012-01-26

    申请号：US12840791

    申请日：2010-07-21

    申请人： Frederick G. Anderson ,  Jenifer E. Lary ,  Robert M. Rassel ,  Mark E. Stidham

    发明人： Frederick G. Anderson ,  Jenifer E. Lary ,  Robert M. Rassel ,  Mark E. Stidham

    IPC分类号： H01L29/872 ,  G06F9/45 ,  H01L21/329

    CPC分类号： H01L29/872 ,  H01L21/761 ,  H01L29/0619 ,  H01L29/0646 ,  H01L29/0692 ,  H01L29/66143

    摘要： A Schottky barrier diode comprises a first-type substrate, a second-type well isolation region on the first-type substrate, and a first-type well region on the second-type well isolation region. With embodiments herein a feature referred to as a perimeter capacitance well junction ring is on the second-type well isolation region. A second-type well region is on the second-type well isolation region. The perimeter capacitance well junction ring is positioned between and separates the first-type well region and the second-type well region. A second-type contact region is on the second-type well region, and a first-type contact region contacts the inner portion of the first-type well region. The inner portion of the first-type well region is positioned within the center of the first-type contact region. Additionally, a first ohmic metallic layer is on the first-type contact region and a second ohmic metallic layer is on the first-type well region. The first ohmic metallic layer contacts the second ohmic metallic layer at a junction that makes up the Schottky barrier of the Schottky barrier diode.

    摘要翻译： 肖特基势垒二极管包括第一类型衬底，第一类型衬底上的第二类型阱隔离区域和第二类型阱隔离区域上的第一类型阱区域。 在这里的实施例中，被称为周边电容阱接合环的特征在第二类型的隔离区域上。 第二类型井区域位于第二类型井隔离区域上。 周边电容阱接合环位于第一类型阱区域和第二类型阱区域之间并分离。 第二类型接触区域位于第二类型阱区域上，并且第一类型接触区域接触第一类型阱区域的内部部分。 第一类型阱区域的内部位于第一类型接触区域的中心内。 此外，第一欧姆金属层位于第一类型接触区域上，第二欧姆金属层位于第一类型阱区域上。 第一欧姆金属层在构成肖特基势垒二极管的肖特基势垒的结处接触第二欧姆金属层。

    METHODS OF FORMING A HYPER-ABRUPT P-N JUNCTION AND DESIGN STRUCTURES FOR AN INTEGRATED CIRCUIT
    79.
    发明申请
    METHODS OF FORMING A HYPER-ABRUPT P-N JUNCTION AND DESIGN STRUCTURES FOR AN INTEGRATED CIRCUIT 有权
    形成用于集成电路的高压P-N结和设计结构的方法

    公开(公告)号：US20100248432A1

    公开(公告)日：2010-09-30

    申请号：US12795108

    申请日：2010-06-07

    申请人： Jeffrey B. Johnson ,  Alvin J. Joseph ,  Robert M. Rassel ,  Yun Shi

    发明人： Jeffrey B. Johnson ,  Alvin J. Joseph ,  Robert M. Rassel ,  Yun Shi

    IPC分类号： H01L21/84 ,  G06F17/50

    CPC分类号： H01L29/93

    摘要： Methods of forming hyper-abrupt p-n junctions and design structures for an integrated circuit containing devices structures with hyper-abrupt p-n junctions. The hyper-abrupt p-n junction is defined in a SOI substrate by implanting a portion of a device layer to have one conductivity type and then implanting a portion of this doped region to have an opposite conductivity type. The counterdoping defines the hyper-abrupt p-n junction. A gate structure carried on a top surface of the device layer operates as a hard mask during the ion implantations to assist in defining a lateral boundary for the hyper-abrupt p-n junction.

    摘要翻译： 形成超突变p-n结的方法和包含具有超突变p-n结的器件结构的集成电路的设计结构。 通过将器件层的一部分注入具有一种导电类型，然后将该掺杂区域的一部分注入具有相反的导电型，在SOI衬底中限定超突变p-n结。 反渗透定义了超突变p-n结。 在离子注入期间，在器件层的顶表面上承载的栅结构作为硬掩模进行操作，以有助于限定超突变p-n结的横向边界。

    Device structures with a hyper-abrupt P-N junction, methods of forming a hyper-abrupt P-N junction, and design structures for an integrated circuit
    80.
    发明授权
    Device structures with a hyper-abrupt P-N junction, methods of forming a hyper-abrupt P-N junction, and design structures for an integrated circuit 失效
    具有超陡P-N结的器件结构，形成超陡P-N结的方法，以及集成电路的设计结构

    公开(公告)号：US07804119B2

    公开(公告)日：2010-09-28

    申请号：US12099316

    申请日：2008-04-08

    申请人： Jeffrey B. Johnson ,  Alvin J. Joseph ,  Robert M. Rassel ,  Yun Shi

    发明人： Jeffrey B. Johnson ,  Alvin J. Joseph ,  Robert M. Rassel ,  Yun Shi

    IPC分类号： H01L27/108

    CPC分类号： H01L29/93

    摘要： Device structures with hyper-abrupt p-n junctions, methods of forming hyper-abrupt p-n junctions, and design structures for an integrated circuit containing devices structures with hyper-abrupt p-n junctions. The hyper-abrupt p-n junction is defined in a SOI substrate by implanting a portion of a device layer to have one conductivity type and then implanting a portion of this doped region to have an opposite conductivity type. The counterdoping defines the hyper-abrupt p-n junction. A gate structure carried on a top surface of the device layer operates as a hard mask during the ion implantations to assist in defining a lateral boundary for the hyper-abrupt-n junction.

    摘要翻译： 具有超突变p-n结的器件结构，形成超突变p-n结的方法以及包含具有超突变p-n结的器件结构的集成电路的设计结构。 通过将器件层的一部分注入具有一种导电类型，然后将该掺杂区域的一部分注入具有相反的导电型，在SOI衬底中限定超突变p-n结。 反渗透定义了超突变p-n结。 在离子注入期间，在器件层的顶表面上承载的栅极结构作为硬掩模进行操作，以有助于限定超突变n结的横向边界。