公开(公告)号：US09601175B2

公开(公告)日：2017-03-21

申请号：US15056486

申请日：2016-02-29

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Syed M. Alam

IPC: G11C7/12 ,  G11C11/16 ,  G11C7/08 ,  G06F12/08 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4094 ,  G11C11/419 ,  G11C11/4091 ,  G11C11/56

CPC classification number: G11C11/1675 ,  G06F12/0806 ,  G06F12/0879 ,  G06F2212/62 ,  G11C7/1018 ,  G11C7/1045 ,  G11C7/12 ,  G11C7/22 ,  G11C11/16 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1693 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/419 ,  G11C11/5607 ,  Y02D10/13

Abstract: In a spin-torque magnetic random access memory (MRAM) that includes local source lines, auto-booting of the word line is used to conserve power consumption by reusing charge already present from driving a plurality of bit lines during writing operations. Auto-booting is accomplished by first driving the word line to a first word line voltage. After such driving, the word line isolated. Subsequent driving of the plurality of bit lines that are capacitively coupled to the word line causes the word line voltage to be increased to a level desired to allow sufficient current to flow through a selected memory cell to write information into the selected memory cell. Additional embodiments include the use of a supplemental voltage provider that is able to further boost or hold the isolated word line at the needed voltage level.

公开(公告)号：US20170060691A1

公开(公告)日：2017-03-02

申请号：US15347307

申请日：2016-11-09

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam ,  Thomas Andre

IPC: G06F11/10 ,  G11C14/00

CPC classification number: G06F11/1096 ,  G06F11/1064 ,  G06F12/0882 ,  G06F2211/109 ,  G06F2212/652 ,  G11C14/0036

Abstract: In some examples, a memory is configured to write multiple pages of an internal page size from a cache on the memory to a memory array on the memory in response to receiving a single precharge command when in a page emulation mode. When in the page emulation mode, the memory also reads multiple pages of the internal page size from the memory array and stores them in the cache in response to receiving a single activate command.

Abstract translation: 在一些示例中，响应于在页面仿真模式中接收到单个预充电命令，存储器被配置为将内部页面大小的页面从存储器上的高速缓存写入存储器上的存储器阵列。 当处于页面仿真模式时，存储器还从存储器阵列读取内部页面大小的多个页面，并响应于接收到单个激活命令将它们存储在高速缓存中。

公开(公告)号：US09543041B2

公开(公告)日：2017-01-10

申请号：US14837381

申请日：2015-08-27

Applicant: Everspin Technologies, Inc.

Inventor： Jason Janesky ,  Syed M. Alam ,  Dimitri Houssameddine ,  Mark Deherrera

IPC: G11C11/34 ,  G11C11/00 ,  G11C29/12 ,  G11C29/02 ,  G11C29/50 ,  G11C11/16

CPC classification number: G11C11/1673 ,  G11C11/16 ,  G11C11/1675 ,  G11C17/16 ,  G11C29/021 ,  G11C29/023 ,  G11C29/026 ,  G11C29/028 ,  G11C29/12 ,  G11C29/50

Abstract: Techniques and circuits for testing and configuring magnetic memory devices are presented. Registers and nonvolatile storage is included on the memory devices for storing values used to control testing of the memory devices as well as for configuring parameters related to both testing and normal operation. Examples include adjustment of bias voltages, sense amplifier offset values, and timing parameters to improve the efficiency of testing operations as well as improve reliability and speed of normal operation.

Abstract translation: 介绍了用于测试和配置磁存储器件的技术和电路。 寄存器和非易失性存储器包含在存储器件中，用于存储用于控制存储器件测试的值以及用于配置与测试和正常操作相关的参数。 示例包括偏置电压的调整，读出放大器偏移值和定时参数，以提高测试操作的效率，以及提高正常操作的可靠性和速度。

公开(公告)号：US20160350031A1

公开(公告)日：2016-12-01

申请号：US15212271

申请日：2016-07-17

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam ,  Thomas Andre ,  Dietmar Gogl

IPC: G06F3/06 ,  G11C11/4091 ,  G11C11/4096 ,  G11C14/00 ,  G11C11/16

CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/0685 ,  G06F12/0246 ,  G06F12/0638 ,  G06F13/1694 ,  G06F2212/205 ,  G06F2212/7201 ,  G11C7/1042 ,  G11C7/1072 ,  G11C8/04 ,  G11C11/005 ,  G11C11/16 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  G11C14/0036

Abstract: A memory system and memory controller for interleaving volatile and non-volatile memory accesses are described. In the memory system, the memory controller is coupled to the volatile and non-volatile memories using a shared address bus. Activate latencies for the volatile and non-volatile memories are different, and registers are included on the memory controller for storing latency values. Additional registers on the memory controller store precharge latencies for the memories as well as page size for the non-volatile memory. A memory access sequencer on the memory controller asserts appropriate chip select signals to the memories to initiate operations therein.

Abstract translation: 描述了用于交织易失性和非易失性存储器访问的存储器系统和存储器控制器。 在存储器系统中，存储器控制器使用共享地址总线耦合到易失性和非易失性存储器。 激活易失性和非易失性存储器的延迟是不同的，寄存器包含在存储器控制器中用于存储延迟值。 存储器控制器上的附加寄存器存储存储器的预充电延迟以及非易失性存储器的页面大小。 存储器控制器上的存储器访问定序器向存储器发出适当的片选信号以启动其中的操作。

公开(公告)号：US09454432B2

公开(公告)日：2016-09-27

申请号：US14737558

申请日：2015-06-12

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam ,  Thomas Andre ,  Matthew R. Croft

IPC: G06F11/10 ,  G11C11/16 ,  H03M13/29

CPC classification number: G06F11/1076 ,  G06F11/1012 ,  G06F11/1048 ,  G11C11/1673 ,  G11C11/1675 ,  H03M13/2906

Abstract: A method includes destructively reading bits of a spin torque magnetic random access memory, using error correcting code (ECC) for error correction, and storing inverted or non-inverted data in data-store latches. When a subsequent write operation changes the state of data-store latches, parity calculation and majority detection of the bits are initiated. A majority bit detection and potential inversion of write data minimizes the number of write current pulses. A subsequent write operation received within a specified time or before an original write operation is commenced will cause the majority detection operation to abort.

公开(公告)号：US09378798B2

公开(公告)日：2016-06-28

申请号：US14970563

申请日：2015-12-16

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam ,  Thomas Andre ,  Matthew R. Croft ,  Chitra Subramanian ,  Halbert Lin

IPC: G11C11/00 ,  G11C11/16

CPC classification number: G11C11/1675 ,  G06F11/1048 ,  G06F11/1076 ,  G11C11/00 ,  G11C11/16 ,  G11C11/1673 ,  G11C11/1693 ,  G11C2013/0076 ,  G11C2029/0411

Abstract: A spin-torque magnetoresistive memory includes array read circuits and array write circuits coupled to an array of magnetic bits. The array read circuits sample magnetic bits in the array, apply a write current pulse to the magnetic bits to set them to a first logic state, resample the magnetic bits, and comparing the results of sampling and resampling to determine the bit state for each magnetic bit. For each of the magnetic bits in the page having the second logic state, the array write circuits initiate a write-back, wherein the write-back includes applying a second write current pulse having opposite polarity in comparison with the first write current pulse to set the magnetic bit to the second state. A read or write operation may be received after initiation of the write-back where the write-back can be aborted for a portion of the bits in the case of a write operation. The write-back may be performed such that different portions of the magnetic bits are written back at different times, thereby staggering the write-back current pulses in time. An offset current may also be used during resampling.

Abstract translation: 自旋转矩磁阻存储器包括耦合到磁头阵列的阵列读取电路和阵列写入电路。 阵列读取电路对阵列中的磁头进行采样，向磁头施加写入电流脉冲以将其设置为第一逻辑状态，对磁头进行重新采样，并比较采样和重采样的结果，以确定每个磁性的位状态 位。 对于具有第二逻辑状态的页面中的每个磁性位，阵列写入电路启动回写，其中写回包括施加与第一写入电流脉冲相比具有相反极性的第二写入电流脉冲以设置 磁头到第二个状态。 在写回开始之后可以接收读取或写入操作，其中在写入操作的情况下可以中止一部分位的写回。 可以执行回写，使得磁头的不同部分在不同的时间被写回，从而及时地交错回写电流脉冲。 在重采样期间也可以使用偏移电流。

公开(公告)号：US20160172019A1

公开(公告)日：2016-06-16

申请号：US15051794

申请日：2016-02-24

Applicant: Everspin Technologies, Inc.

Inventor： Dietmar Gogl ,  Syed M. Alam ,  Thomas Andre ,  Halbert S. Lin

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C8/08 ,  G11C11/1657 ,  G11C11/1693 ,  G11C11/1697

Abstract: A boosted supply voltage generator is selectively activated and deactivated to allow operations that are sensitive to variations on the boosted voltage to be performed with a stable boosted voltage. Techniques for deactivating and reactivating the voltage generator are also disclosed that enable more rapid recovery from deactivation such that subsequent operations can be commenced sooner. Such techniques include storing state information corresponding to the voltage generator when deactivated, where the stored state information is used when reactivating the voltage generator. Stored state information can include a state of a clock signal provided to the voltage generator.

Abstract translation: 升压的电源电压发生器被选择性地激活和去激活，以允许以稳定的升压电压来执行对升压电压的变化敏感的操作。 还公开了用于停用和重新激活电压发生器的技术，其使得能够从停用中更快速地恢复，使得可以更快地开始后续操作。 这样的技术包括当停用时存储对应于电压发生器的状态信息，其中在重新激活电压发生器时使用存储的状态信息。 存储状态信息可以包括提供给电压发生器的时钟信号的状态。

公开(公告)号：US20160093341A1

公开(公告)日：2016-03-31

申请号：US14496984

申请日：2014-09-25

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam ,  Thomas Andre

IPC: G11C5/06 ,  G11C7/12 ,  G11C7/06

CPC classification number: G11C7/12 ,  G11C5/063 ,  G11C7/062

Abstract: In some examples, a memory device may have at least a first and a second memory array. In some cases, a portion of the bit cells of the first memory array may be coupled to first PMOS-follower circuitry and to second PMOS-follower circuitry. A portions of the bit cells of the second memory array may also be coupled to the second PMOS-follower circuitry and to third PMOS-follower circuitry. Additionally, in some cases, the portion of bit cells of both the first memory array and the second memory array may be coupled to shared preamplifier circuitry.

Abstract translation: 在一些示例中，存储器件可以具有至少第一和第二存储器阵列。 在一些情况下，第一存储器阵列的位单元的一部分可以耦合到第一PMOS跟随器电路和第二PMOS跟随器电路。 第二存储器阵列的位单元的一部分也可以耦合到第二PMOS跟随器电路和第三PMOS跟随器电路。 另外，在一些情况下，第一存储器阵列和第二存储器阵列的位单元的部分可以耦合到共享前置放大器电路。

公开(公告)号：US20160092305A1

公开(公告)日：2016-03-31

申请号：US14496964

申请日：2014-09-25

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam ,  Thomas Andre

IPC: G06F11/10

CPC classification number: H03M13/2906 ,  G06F11/1012 ,  G06F11/1076

Abstract: In some examples, a memory device includes memory arrays configured to store pages of data organized into multiple ECC words. The memory device also includes at least one input/output pad for each ECC word associated with a page, such that a first level of error correction may be performed by the memory device on each of the ECC words associated with a page and a second level of error correction may be performed on the data output by each of the input/output pads during a particular period of time. Each of the one or more input/output pads of the memory device may be configured to provide only one bit of data per ECC word to an external source during an access from an external source.

Abstract translation: 在一些示例中，存储器设备包括被配置为存储组织成多个ECC字的数据页的存储器阵列。 存储装置还包括用于与页面相关联的每个ECC字的至少一个输入/输出焊盘，使得存储器装置可以在与页面和第二级相关联的每个ECC字上执行第一级错误校正 可以在特定时间段内对每个输入/输出焊盘输出的数据执行纠错。 存储器件的一个或多个输入/输出焊盘中的每一个可被配置为在从外部源访问期间仅向外部源提供每个ECC字的一位数据。

公开(公告)号：US20160027489A1

公开(公告)日：2016-01-28

申请号：US14878461

申请日：2015-10-08

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam ,  Thomas Andre ,  Chitra Subramanian

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C11/1675 ,  G11C13/004 ,  G11C2013/0057

Abstract: A method of reading data from a plurality of bits in a spin-torque magnetoresistive memory array includes performing one or more referenced read operations of the bits, and performing a self-referenced read operation, for example, a destructive self-referenced read operation, of any of the bits not successfully read by the referenced read operation. The referenced read operations can be initiated at the same time or prior to that of the destructive self-referenced read operation.