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    TRENCH SILICIDE CONTACTS WITH HIGH SELECTIVITY PROCESS
    76.
    发明申请
    TRENCH SILICIDE CONTACTS WITH HIGH SELECTIVITY PROCESS 审中-公开

    公开(公告)号：US20170125292A1

    公开(公告)日：2017-05-04

    申请号：US15190778

    申请日：2016-06-23

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

    Inventor： Andrew M. Greene ,  Balasubramanian Pranatharthiharan ,  Ruilong Xie

    IPC: H01L21/768 ,  H01L29/66 ,  H01L23/532 ,  H01L29/78 ,  H01L23/535

    Abstract: A method for forming self-aligned contacts includes patterning a mask between fin regions of a semiconductor device, etching a cut region through a first dielectric layer between the fin regions down to a substrate and filling the cut region with a first material, which is selectively etchable relative to the first dielectric layer. The first dielectric layer is isotropically etched to reveal source and drain regions in the fin regions to form trenches in the first material where the source and drain regions are accessible. The isotropic etching is super selective to remove the first dielectric layer relative to the first material and relative to gate structures disposed between the source and drain regions. Metal is deposited in the trenches to form silicide contacts to the source and drain regions.

    Method to prevent lateral epitaxial growth in semiconductor devices
    77.
    发明授权
    Method to prevent lateral epitaxial growth in semiconductor devices 有权
    防止半导体器件中横向外延生长的方法

    公开(公告)号：US09590074B1

    公开(公告)日：2017-03-07

    申请号：US14960380

    申请日：2015-12-05

    Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

    Inventor： Balasubramanian Pranatharthiharan ,  Hui Zang

    IPC: H01L21/00 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/762 ,  H01L21/311 ,  H01L27/11 ,  H01L21/027 ,  H01L21/822 ,  H01L29/78 ,  H01L21/304 ,  H01L21/324

    CPC classification number: H01L27/1104 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/02642 ,  H01L21/3043 ,  H01L21/324 ,  H01L21/76 ,  H01L21/76224 ,  H01L21/8221 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/1116 ,  H01L28/00 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

    Abstract: The method for preventing epitaxial growth in a semiconductor device begins with patterning a photoresist layer over a semiconductor structure having a set of fin ends on a set of fins of a FinFET structure. The set of fins are isolated from one another by a first dielectric material. The photoresist is patterned over the set of fin ends so that it differs from the photoresist pattern over other areas of the FinFET structure. A set of dielectric blocks is formed on the set of fin ends using the photoresist pattern. The set of dielectric blocks prevents epitaxial growth at the set of fin ends in a subsequent epitaxial growth step. In another aspect of the invention, a semiconductor device includes a set of fin structures having a set of fin ends at a respective vertical surface of a fin structure and is separated by a set of trenches from other fin structures. Each of the fin structures has a top surface which is higher than a top surface of a dielectric material in the set of trenches. A set of dielectric blocks is disposed at the set of fin ends, the dielectric blocks having a top surface level with or above the top surfaces of the fin structures which inhibit excessive epitaxial growth at the fin ends.

    Abstract translation: 用于防止半导体器件中的外延生长的方法开始于在FinFET结构的一组鳍片上具有一组翅片端的半导体结构上的光致抗蚀剂层图案化。 翅片组通过第一介电材料彼此隔离。 光致抗蚀剂被图案化在鳍片端部上，使得其与FinFET结构的其它区域上的光致抗蚀剂图案不同。 使用光致抗蚀剂图案在一组翅片端部上形成一组介质块。 所述介电块组在随后的外延生长步骤中防止在所述鳍片端部的外延生长。 在本发明的另一方面，一种半导体器件包括一组翅片结构，其鳍片结构的相应垂直表面具有一组翅片端，并且由一组沟槽与其它翅片结构隔开。 每个翅片结构具有比该组沟槽中的电介质材料的顶表面高的顶表面。 一组介电块设置在翅片端部的集合处，所述介电块具有与翅片结构的顶表面上或上方的顶表面水平，所述顶部表面限制在翅片端部处的过度的外延生长。

    Methods of forming FinFET semiconductor devices with self-aligned contact elements using a replacement gate process and the resulting devices
    79.
    发明授权
    Methods of forming FinFET semiconductor devices with self-aligned contact elements using a replacement gate process and the resulting devices 有权
    使用替代栅极工艺形成具有自对准接触元件的FinFET半导体器件的方法以及所得到的器件

    公开(公告)号：US09515163B2

    公开(公告)日：2016-12-06

    申请号：US14021594

    申请日：2013-09-09

    Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

    Inventor： Ruilong Xie ,  Shom Ponoth ,  Balasubramanian Pranatharthiharan

    IPC: H01L29/66 ,  H01L29/78 ,  H01L29/417

    CPC classification number: H01L29/66545 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

    Abstract: One method disclosed herein includes removing a sacrificial gate structure and forming a replacement gate structure in its place, after forming the replacement gate structure, forming a metal silicide layer on an entire upper surface area of each of a plurality of source/drain regions and, with the replacement gate structure in position, forming at least one source/drain contact structure for each of the plurality of source/drain regions, wherein the at least one source/drain contact structure is conductively coupled to a portion of the metal silicide layer and a dimension of the at least one source/drain contact structure in a gate width direction of the transistor is less than a dimension of the source/drain region in the gate width direction.

    Abstract translation: 本文公开的一种方法包括在形成替代栅极结构之后，移除牺牲栅极结构并形成替代栅极结构，在多个源极/漏极区中的每一个的整个上表面区域上形成金属硅化物层， 其中所述替换栅极结构处于适当位置，为所述多个源极/漏极区域中的每一个形成至少一个源极/漏极接触结构，其中所述至少一个源极/漏极接触结构导电耦合到所述金属硅化物层的一部分，以及 晶体管的栅极宽度方向上的至少一个源极/漏极接触结构的尺寸小于栅极宽度方向上的源极/漏极区域的尺寸。

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