公开(公告)号：US20180323298A1

公开(公告)日：2018-11-08

申请号：US15773422

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： Sansaptak DASGUPTA ,  Han Wui THEN ,  Marko RADOSAVLJEVIC

IPC: H01L29/778 ,  H01L29/423 ,  H01L29/08 ,  H01L29/20 ,  H01L29/06 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/7788 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/02647 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0843 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/78

Abstract: III-N transistor including a vertically-oriented lightly-doped III-N drift region between an overlying III-N 2DEG channel and an underlying heavily-doped III-N drain. In some embodiments, the III-N transistors are disposed over a silicon substrate. In some embodiments, lateral epitaxial overgrowth is employed to form III-N islands self-aligned with the vertically-oriented drift region. A gate electrode disposed over a portion of a III-N island may modulate a 2DEG within a channel region of the III-N island disposed above the III-N drift region. Charge carriers in the 2DEG channel may be swept into the drift region toward the drain. Topside contacts to each of the gate, source, and drain may be pitch scaled independently of a length of the drift region.

公开(公告)号：US20170012117A1

公开(公告)日：2017-01-12

申请号：US15120496

申请日：2014-03-21

Applicant: INTEL CORPORATION

Inventor： Marko RADOSAVLJEVIC ,  Brian S. DOYLE ,  Ravi PILLARISETTY ,  Niloy MUKHERJEE ,  Sansaptak DASGUPTA ,  Han Wui THEN ,  Robert S. CHAU

IPC: H01L29/778 ,  H01L21/8256 ,  H01L29/66 ,  H01L27/12 ,  H01L29/24 ,  H01L21/02

CPC classification number: H01L29/7782 ,  H01L21/02422 ,  H01L21/02568 ,  H01L21/8256 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/0843 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/786 ,  H01L29/78603 ,  H01L29/78681

Abstract: Embodiments of semiconductor assemblies, and related integrated circuit devices and techniques, are disclosed herein. In some embodiments, a semiconductor assembly may include a flexible substrate, a first barrier formed of a first transition metal dichalcogenide (TMD) material, a transistor channel formed of a second TMD material, and a second barrier formed of a third TMD material. The first barrier may be disposed between the transistor channel and the flexible substrate, the transistor channel may be disposed between the second barrier and the first barrier, and a bandgap of the transistor channel may be less than a bandgap of the first barrier and less than a bandgap of the second barrier. Other embodiments may be disclosed and/or claimed.

Abstract translation: 本文公开了半导体组件的实施例以及相关的集成电路器件和技术。 在一些实施例中，半导体组件可以包括柔性衬底，由第一过渡金属二硫属元素（TMD）材料形成的第一阻挡层，由第二TMD材料形成的晶体管沟道和由第三TMD材料形成的第二阻挡层。 第一势垒可以设置在晶体管沟道和柔性衬底之间，晶体管沟道可以设置在第二栅极和第一势垒之间，晶体管沟道的带隙可能小于第一势垒的带隙，而小于 第二个屏障的带隙。 可以公开和/或要求保护其他实施例。

公开(公告)号：US20160276438A1

公开(公告)日：2016-09-22

申请号：US15036406

申请日：2013-12-23

Applicant: INTEL CORPORATION

Inventor： Benjamin CHU-KUNG ,  Sherry R. TAFT ,  Van H. LE ,  Sansaptak DASGUPTA ,  Seung Hoon Hoon SUNG ,  Sanaz K. GARDNER ,  Matthew V. METZ ,  Marko RADOSAVLJEVIC ,  Han Wui THEN

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/161 ,  H01L29/20

CPC classification number: H01L29/1037 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/2003 ,  H01L29/66795

Abstract: Techniques are disclosed for forming a defect-free semiconductor structure on a dissimilar substrate with a multi-aspect ratio mask. The multi-aspect ratio mask comprises a first, second, and third layer formed on a substrate. The second layer has a second opening wider than a first opening and a third opening in the first and third layers, respectively. All three openings are centered along a common central axis. A semiconductor material is grown from the top surface of the substrate and laterally onto the top surface of the first layer within the second opening. The semiconductor material disposed within and vertically below the third opening is etched by using the third layer as an etch mask so that the remaining material that laterally overflowed onto the top surface of the first layer forms a remaining structure.

Abstract translation: 公开了用于在具有多纵横比掩模的不同基板上形成无缺陷半导体结构的技术。 多纵横比掩模包括形成在基板上的第一，第二和第三层。 第二层分别具有比第一和第三层中的第一开口和第三开口更宽的第二开口。 所有三个开口沿着共同的中心轴线居中。 半导体材料从衬底的顶表面生长并横向放置在第二开口内的第一层的顶表面上。 通过使用第三层作为蚀刻掩模来蚀刻设置在第三开口内并垂直于第三开口下方的半导体材料，使得横向溢出到第一层的顶表面上的剩余材料形成剩余结构。

公开(公告)号：US20240222438A1

公开(公告)日：2024-07-04

申请号：US18089945

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Han Wui THEN ,  Tahir GHANI ,  Anand S. MURTHY ,  Wilfred GOMES ,  Sagar SUTHRAM ,  Pushkar RANADE

IPC: H01L29/26 ,  H01L29/36 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/26 ,  H01L29/36 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66462 ,  H01L29/7787

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for designing and fabricating semiconductor packages that include transistors that include wide band gap materials, such as silicon carbide or gallium nitride. Other embodiments may be described and/or claimed.

公开(公告)号：US20240222435A1

公开(公告)日：2024-07-04

申请号：US18089936

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Han Wui THEN ,  Wilfred GOMES ,  Anand S. MURTHY ,  Tahir GHANI ,  Sagar SUTHRAM ,  Pushkar RANADE

IPC: H01L29/16 ,  H01L21/02 ,  H01L27/105

CPC classification number: H01L29/1608 ,  H01L21/02447 ,  H01L21/02529 ,  H01L27/105

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for fabricating semiconductor packages that use a SiC layer that is coupled with another layer that includes another material. The SiC layer may be an active layer that includes devices, such as transistors, that are coupled with devices that may be in the other layer. The SiC layer may be coupled with the other layer using fusion bonding, hybrid bonding, layer transfer, and/or bump and island formation techniques. Other embodiments may be described and/or claimed.

公开(公告)号：US20240213140A1

公开(公告)日：2024-06-27

申请号：US18088541

申请日：2022-12-24

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Samuel James BADER ,  Ahmad ZUBAIR ,  Pratik KOIRALA ,  Michael S. BEUMER ,  Heli Chetanbhai VORA ,  Ibrahim BAN ,  Nityan NAIR ,  Thomas HOFF

IPC: H01L23/522 ,  H01L23/48

CPC classification number: H01L23/5223 ,  H01L23/481 ,  H01L23/5226

Abstract: Structures having backside high voltage capacitors for front side GaN-based devices are described. In an example, an integrated circuit structure includes a front side structure including a GaN-based device layer, and one or more metallization layers above the GaN-based device layer. A backside structure is below and coupled to the GaN-based layer, the backside structure including metal layers and one or more alternating laterally-recessed metal insulator metal capacitors.

公开(公告)号：US20240203815A1

公开(公告)日：2024-06-20

申请号：US18085106

申请日：2022-12-20

Applicant: Intel Corporation

Inventor： Samuel James BADER ,  Nachiket Venkappayya DESAI ,  Han Wui THEN

IPC: H01L23/34 ,  H01L29/20 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L23/34 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/66462 ,  H01L29/7786

Abstract: Layer transfer for Gallium nitride (GaN) integrated circuit technology is described. In an example, an integrated circuit structure includes a GaN device on or above a substrate, the GaN device including a source, a gate and a drain. A silicon-based diode structure or a silicon-based thin-film resistor is above the substrate, the silicon-based diode structure or the silicon-based thin-film resistor over the GaN device in a region between the gate and the drain of the GaN device.

公开(公告)号：US20230057992A1

公开(公告)日：2023-02-23

申请号：US17406296

申请日：2021-08-19

Applicant: Intel Corporation

Inventor： Tanay GOSAVI ,  Raseong KIM ,  Han Wui THEN ,  Ian A. YOUNG

IPC: H01L27/20 ,  H01L29/20 ,  H01L29/778 ,  H03H9/02 ,  H03H9/17 ,  H01L29/66 ,  H03H3/02

Abstract: Gallium nitride (GaN) integrated circuit technology with resonators is described. In an example, an integrated circuit structure includes a layer or substrate including gallium and nitrogen. A first plurality of electrodes is over the layer or substrate. A resonator layer is on the first plurality of electrodes, the resonator layer including aluminum and nitrogen. A second plurality of electrodes is on the resonator layer. Individual ones of the second plurality of electrodes are vertically over and aligned with corresponding individual ones of the first plurality of electrodes.

公开(公告)号：US20210167200A1

公开(公告)日：2021-06-03

申请号：US16645119

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Marko RADOSAVLJEVIC ,  Sansaptak DASGUPTA ,  Han Wui THEN

IPC: H01L29/778 ,  H01L29/417 ,  H01L29/51 ,  H01L21/8252 ,  H01L29/40

Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device that may include an III-V transistor with a resistive gate contact. A semiconductor device may include a substrate, and a channel base including a layer of GaN above the substrate. A channel stack may be above the channel base, and may include a layer of GaN in the channel stack, and a polarization layer above the layer of GaN in the channel stack. A gate stack may be above the channel stack, where the gate stack may include a gate dielectric layer above the channel stack, and a resistive gate contact above the gate dielectric layer. The resistive gate contact may include silicon (Si) or germanium (Ge). Other embodiments may be described and/or claimed.

公开(公告)号：US20200227396A1

公开(公告)日：2020-07-16

申请号：US15754822

申请日：2015-09-24

Applicant: Intel Corporation

Inventor： Sansaptak W. DASGUPTA ,  Marko RADOSAVLJEVIC ,  Han Wui THEN ,  Ravi PILLARISETTY ,  Kimin JUN ,  Patrick MORROW ,  Valluri R. RAO ,  Paul B. FISCHER ,  Robert S. CHAU

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L21/78 ,  H01L25/00

Abstract: The electrical and electrochemical properties of various semiconductors may limit the usefulness of various semiconductor materials for one or more purposes. A completed gallium nitride (GaN) semiconductor layer containing a number of GaN power management integrated circuit (PMIC) dies may be bonded to a completed silicon semiconductor layer containing a number of complementary metal oxide (CMOS) control circuit dies. The completed GaN layer and the completed silicon layer may be full size (e.g., 300 mm). A layer transfer operation may be used to bond the completed GaN layer to the completed silicon layer. The layer transfer operation may be performed on full size wafers. After slicing the full size wafers a large number of multi-layer dies, each having a GaN die layer transferred to a silicon die may be produced.