公开(公告)号：US10438659B2

公开(公告)日：2019-10-08

申请号：US16037255

申请日：2018-07-17

Applicant: Intel Corporation

Inventor： Balaji Srinivasan ,  Daniel Chu ,  Lark-Hoon Leem ,  John Gorman ,  Mase Taub ,  Sandeep Guliani ,  Kiran Pangal

IPC: G11C13/00

Abstract: In one embodiment, an apparatus comprises read circuitry to apply a read voltage to a three dimensional crosspoint (3DXP) memory cell; and write setback circuitry to apply a first setback pulse having a first magnitude to the 3DXP memory cell in response to the application of the read voltage, wherein applying the first setback pulse comprises bypassing a current mirror that is to limit or control a magnitude of a second setback pulse applied to the 3DXP memory cell when the current mirror is coupled to the 3DXP memory cell.

公开(公告)号：US10331345B2

公开(公告)日：2019-06-25

申请号：US15721394

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Wei Fang ,  Kiran Pangal ,  Prashant S. Damle

IPC: G11C16/28 ,  G06F3/06 ,  G06F13/16 ,  G06F11/10 ,  G06F12/02

Abstract: In one embodiment, an apparatus comprises a memory array comprising a plurality of phase change memory (PCM) cells; and a controller to determine to read data stored by the plurality of PCM cells independent of a read command from a host device; and in response to the determination to read data stored by the plurality of PCM cells independent of a read command from a host device, perform a dummy read operation on the plurality of PCM cells and perform an additional read operation on the plurality of PCM cells.

公开(公告)号：US10269396B2

公开(公告)日：2019-04-23

申请号：US16036756

申请日：2018-07-16

Applicant: Intel Corporation

Inventor： Rakesh Jeyasingh ,  Nevil N Gajera ,  Mase J. Taub ,  Kiran Pangal

IPC: G11C13/00 ,  G11C7/12 ,  G11C11/16 ,  G11C11/56

Abstract: Examples may include techniques to mitigate bias drift for memory cells of a memory device. A first memory cell coupled with a first word-line and a bit-line is selected for a write operation. A second memory cell coupled with a second word-line and the bit-line is de-selected for the write operation. First and second bias voltages are applied to the first word-line and the bit-line during the write operation to program the first memory cell. A third bias voltage is applied to the second word-line during the write operation to reduce or mitigate voltage bias to the second memory cell due to the second bias voltage applied to the bit-line to program the first memory cell.

公开(公告)号：US20190102088A1

公开(公告)日：2019-04-04

申请号：US15721394

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Wei Fang ,  Kiran Pangal ,  Prashant S. Damle

IPC: G06F3/06 ,  G06F12/02 ,  G06F13/16 ,  G06F11/10

CPC classification number: G06F3/0602 ,  G06F3/0653 ,  G06F3/0683 ,  G06F11/1044 ,  G06F12/0246 ,  G06F13/1668 ,  G06F2003/0697

Abstract: In one embodiment, an apparatus comprises a memory array comprising a plurality of phase change memory (PCM) cells; and a controller to determine to read data stored by the plurality of PCM cells independent of a read command from a host device; and in response to the determination to read data stored by the plurality of PCM cells independent of a read command from a host device, perform a dummy read operation on the plurality of PCM cells and perform an additional read operation on the plurality of PCM cells.

公开(公告)号：US10056136B2

公开(公告)日：2018-08-21

申请号：US15614141

申请日：2017-06-05

Applicant: Intel Corporation

Inventor： Mase J. Taub ,  Sandeep K. Guliani ,  Kiran Pangal

IPC: G11C11/00 ,  G11C13/00 ,  G11C5/02

CPC classification number: G11C13/0004 ,  G11C5/02 ,  G11C7/00 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/77

Abstract: A system and technique is disclosed for writing data in a cross-point memory. The state of one or more memory cells of the cross-point memory are sensed and then are continued to be selected and left on. It is then determined which of the one or more memory cells are to change state based on incoming user data that is to be written into the one or more memory cells. The one or more memory cells determined to change state and are still selected to be on are then written by applying a write-current pulse to the memory cells. In one exemplary embodiment, the one or more memory cells comprise one or more phase-change-type memory cell devices.

公开(公告)号：US09934088B2

公开(公告)日：2018-04-03

申请号：US14844843

申请日：2015-09-03

Applicant: Intel Corporation

Inventor： Kiran Pangal ,  Prashant S. Damle ,  Rajesh Sundaram ,  Shekoufeh Qawami ,  Julie M. Walker ,  Doyle Rivers

IPC: H03M13/00 ,  G06F11/10 ,  H03M13/05 ,  H03M13/27 ,  G06F3/06 ,  H03M13/15 ,  H03M13/19

CPC classification number: G06F11/1076 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1044 ,  G06F11/1048 ,  G06F11/1068 ,  H03M13/05 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/19 ,  H03M13/27 ,  H03M13/6508

Abstract: Uncorrectable memory errors may be reduced by determining a logical array address for a set of memory arrays and transforming the logical array address to at least two unique array addresses based, at least in part, on logical locations of at least two memory arrays within the set of memory arrays. The at least two memory arrays are then accessed using the at least two unique array addresses, respectively.

公开(公告)号：US09892785B2

公开(公告)日：2018-02-13

申请号：US15442594

申请日：2017-02-24

Applicant: Intel Corporation

Inventor： Sanjay Rangan ,  Kiran Pangal ,  Nevil N Gajera ,  Lu Liu ,  Gayathri Rao Subbu

IPC: G11C11/16 ,  G11C13/00 ,  H01L45/00

CPC classification number: G11C13/0069 ,  G11C7/04 ,  G11C11/16 ,  G11C13/0004 ,  G11C13/0061 ,  G11C2013/0078 ,  G11C2013/008 ,  G11C2013/0092 ,  H01L45/06 ,  H01L45/1286 ,  H01L45/141

Abstract: Phase change material can be set with a multistage set process. Set control logic can heat a phase change semiconductor material (PM) to a first temperature for a first period of time. The first temperature is configured to promote nucleation of a crystalline state of the PM. The control logic can increase the temperature to a second temperature for a second period of time. The second temperature is configured to promote crystal growth within the PM. The nucleation and growth of the crystal set the PM to the crystalline state. The multistage ramping up of the temperature can improve the efficiency of the set process relative to traditional approaches.

公开(公告)号：US09857992B2

公开(公告)日：2018-01-02

申请号：US15076963

申请日：2016-03-22

Applicant: Intel Corporation

Inventor： Kiran Pangal ,  Ravi J. Kumar

IPC: G11C29/02 ,  G11C29/50 ,  G11C29/10 ,  G11C29/04 ,  G06F3/06 ,  G06F11/10 ,  G06F11/20 ,  G11C11/56 ,  G11C16/14 ,  G11C16/26 ,  G11C16/34 ,  G11C29/52 ,  G11C16/00

CPC classification number: G06F3/0616 ,  G06F3/064 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/1068 ,  G06F11/2094 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/00 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3436 ,  G11C29/021 ,  G11C29/026 ,  G11C29/028 ,  G11C29/50016 ,  G11C29/52 ,  G11C2029/0401

Abstract: Methods and apparatus to provide dynamic window to improve NAND (Not And) memory endurance are described. In one embodiment, a program-erase window associated with a NAND memory device is dynamically varied by starting with a higher erase verify (TEV) voltage and lowering the TEV voltage with subsequent cycles over a life of the NAND memory device based on a current cycle count value. Alternatively, the program-erase window is dynamically varied by starting with a higher erase verify (PV) voltage and erase verify (TEV) voltage and lowering the PV and TEV voltages with subsequent cycles over a life of the NAND memory device based on the current cycle count value. Other embodiments are also disclosed and claimed.

公开(公告)号：US09792986B2

公开(公告)日：2017-10-17

申请号：US14725826

申请日：2015-05-29

Applicant: Intel Corporation

Inventor： Mase J. Taub ,  Sandeep K. Guliani ,  Kiran Pangal ,  Raymond W. Zeng

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C2213/72 ,  G11C2213/76 ,  G11C2213/79

Abstract: The present disclosure relates to phase change memory current. An apparatus includes a memory controller including a word line (WL) control module and a bit line (BL) control module, the memory controller is to initiate selection of a memory cell. The apparatus further includes a mitigation module to configure a first line selection logic to reduce a transient energy dissipation of the memory cell, the transient energy related to selecting the memory cell.

公开(公告)号：US20170287533A1

公开(公告)日：2017-10-05

申请号：US15415690

申请日：2017-01-25

Applicant: Intel Corporation

Inventor： Rakesh Jeyasingh ,  Nevil N. Gajera ,  Mase J. Taub ,  Kiran Pangal

IPC: G11C7/12

CPC classification number: G11C7/12 ,  G11C11/1657 ,  G11C11/1675 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/0033 ,  G11C13/0069 ,  G11C2213/77

Abstract: Examples may include techniques to mitigate bias drift for memory cells of a memory device. A first memory cell coupled with a first word-line and a bit-line is selected for a write operation. A second memory cell coupled with a second word-line and the bit-line is de-selected for the write operation. First and second bias voltages are applied to the first word-line and the bit-line during the write operation to program the first memory cell. A third bias voltage is applied to the second word-line during the write operation to reduce or mitigate voltage bias to the second memory cell due to the second bias voltage applied to the bit-line to program the first memory cell.