公开(公告)号：US20240222298A1

公开(公告)日：2024-07-04

申请号：US18091583

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Jeremy D. Ecton ,  Brandon Christian Marin ,  Srinivas V. Pietambaram ,  Suddhasattwa Nad ,  Gang Duan

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L24/08 ,  H01L23/49816 ,  H01L23/5381 ,  H01L24/05 ,  H01L24/80 ,  H01L25/0655 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/08225 ,  H01L2224/80444 ,  H01L2224/8049 ,  H01L2924/0105 ,  H01L2924/0132

Abstract: Technologies for die recycling for high yield packaging is disclosed. In the illustrative embodiment, a release layer is deposited on one or more dies. The release layer includes conductive pads and a dielectric layer. Both the conductive pads and the dielectric layer have melting points between a temperature at which the die assembly will be processed and a temperature at which the die may sustain damage. One or more layers such as redistribution layers are deposited on the release layer. If a fault is discovered in the redistribution layers, the die assembly can be heated up past the melting point of the release layer, allowing the die to be removed. The die can then be cleaned and recycled for another packaging attempt.

公开(公告)号：US20240222293A1

公开(公告)日：2024-07-04

申请号：US18091616

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Kristof Darmawikarta ,  Srinivas V. Pietambaram ,  Gang Duan ,  Siddharth Alur Narasimha Krishna ,  Sameer R. Paital ,  Helme A. Castro De la Torre

IPC: H01L23/58 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L23/58 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827

Abstract: Technologies for ribbon field-effect transistors with variable fin numbers are disclosed. In an illustrative embodiment, a stack of semiconductor fins is formed, with each semiconductor fin having a source region, a channel region, and a drain region. Some or all of the channel regions can be selectively removed, allowing for the drive and/or leakage current to be tuned. In some embodiments, one or more of the semiconductor fins near the top of the stack can be removed. In other embodiments, one or more of the semiconductor fins at or closer to the bottom of the stack can be removed.

公开(公告)号：US20240222279A1

公开(公告)日：2024-07-04

申请号：US18091560

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Jeremy D. Ecton ,  Brandon Christian Marin ,  Srinivas V. Pietambaram ,  Gang Duan ,  Suddhasattwa Nad

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L23/15 ,  H01L23/42 ,  H01L23/48 ,  H01L25/00 ,  H01L25/16 ,  H01L25/18

CPC classification number: H01L23/5381 ,  H01L21/481 ,  H01L23/15 ,  H01L23/42 ,  H01L23/481 ,  H01L23/5384 ,  H01L24/08 ,  H01L25/167 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145

Abstract: Technologies for a vertically interconnected glass layer architecture is disclosed. In the illustrative embodiment, an integrated circuit component includes several integrated circuit dies and a glass layer. Integrated circuit dies are positioned both above and below the glass layer. The glass layer has a bridge die embedded in a cavity. The bridge die provides interconnects between the various dies and to other components off of the integrated circuit component. The glass layer can enable three-dimensional heterogeneous integration, allowing for fine pitch connections between dies.

公开(公告)号：US20240186227A1

公开(公告)日：2024-06-06

申请号：US18061181

申请日：2022-12-02

Applicant: Intel Corporation

Inventor： Haobo Chen ,  Bohan Shan ,  Kyle J. Arrington ,  Kristof Darmawikarta ,  Gang Duan ,  Jeremy D. Ecton ,  Hongxia Feng ,  Xiaoying Guo ,  Ziyin Lin ,  Brandon Christian Marin ,  Srinivas V. Pietambaram ,  Dingying Xu

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/538 ,  H01L23/64 ,  H01L25/065 ,  H05K1/02 ,  H05K1/03 ,  H05K1/11 ,  H05K1/18 ,  H05K3/46

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/642 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0655 ,  H05K1/0271 ,  H05K1/0306 ,  H05K1/113 ,  H05K1/181 ,  H05K3/4605 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15174 ,  H01L2924/157 ,  H01L2924/15788 ,  H05K2201/0195

Abstract: In one embodiment, an integrated circuit package substrate includes a core layer comprising a plurality of metal vias electrically coupling a first side of the core layer and a second side of the core layer opposite the first side. The package substrate further includes a build-up layer on the first side of the core layer, the build-up layer comprising metal vias within a dielectric material and electrically connected to the metal vias of the core layer. The dielectric material includes Silicon, Oxygen, and at least one of Boron or Phosphorus.

公开(公告)号：US20240176085A1

公开(公告)日：2024-05-30

申请号：US18059074

申请日：2022-11-28

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Brandon C. Marin ,  Srinivas V. Pietambaram ,  Gang Duan ,  Suddhasattwa Nad

IPC: G02B6/43 ,  G02B6/122 ,  G02B6/30

CPC classification number: G02B6/43 ,  G02B6/122 ,  G02B6/30

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a photonic assembly may include a substrate having a core with a surface, wherein a material of the core includes glass; and a dielectric material on a portion of the surface of the core, the dielectric material including conductive pathways; a photonic integrated circuit (PIC) electrically coupled to the conductive pathways in the dielectric material; a first optical component between the PIC and the surface of the core, wherein the first optical component is along a perimeter of the core; and a second optical component coupled to the first optical component, wherein the second optical component is optically coupled to the PIC by an optical pathway through the first optical component.

公开(公告)号：US20240170351A1

公开(公告)日：2024-05-23

申请号：US17992010

申请日：2022-11-22

Applicant: Intel Corporation

Inventor： Jeremy D. Ecton ,  Gang Duan ,  Brandon Christian Marin ,  Suddhasattwa Nad ,  Srinivas V. Pietambaram

IPC: H01L23/13 ,  H01L21/48 ,  H01L23/00 ,  H01L23/15 ,  H01L23/498 ,  H01L23/538 ,  H01L25/16

CPC classification number: H01L23/13 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/15 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5381 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L25/167 ,  H01L23/49833 ,  H01L23/5385 ,  H01L2224/1601 ,  H01L2224/16057 ,  H01L2224/1607 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2224/17055 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/1511 ,  H01L2924/15153 ,  H01L2924/15174 ,  H01L2924/15788

Abstract: Architectures and processes for redistribution layers in a dielectric cavity to enable an embedded component in semiconductor packaging. The architectures pattern redistribution layers (RDL) over a thick seed and remove dielectric material from the RDL conductive contacts to create the dielectric cavity. The architectures enable 2-sided connections for embedded components in the dielectric cavity with minimal disruption to existing process infrastructure. Such an approach can be used not only for integration of photonic devices, but also for any semiconductor packaging requiring dual sided connection within a dielectric cavity.

公开(公告)号：US20240128181A1

公开(公告)日：2024-04-18

申请号：US18047033

申请日：2022-10-17

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Brandon C. Marin ,  Srinivas V. Pietambaram ,  Hiroki Tanaka ,  Haobo Chen

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/14 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/145 ,  H01L23/49822 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L25/0655 ,  H01L24/32 ,  H01L2924/15311

Abstract: Embodiments of a microelectronic assembly that includes: a package substrate comprising a plurality of layers of organic dielectric material and conductive traces alternating with conductive vias in alternate layers of the organic dielectric material; and a plurality of integrated circuit dies coupled to a first side of the package substrate by interconnects, in which: the plurality of layers of the organic dielectric material comprises at least a first layer having a conductive via and a second layer having a conductive trace in contact with the conductive via, the second layer is not coplanar with the first layer, sidewalls of the conductive via are orthogonal to the conductive trace, and two opposing sidewalls of the conductive via separated by a width of the conductive via protrude from respectively proximate edges of the conductive trace by a protrusion that is at least ten times less than the width of the conductive via.

公开(公告)号：US20240114627A1

公开(公告)日：2024-04-04

申请号：US17937894

申请日：2022-10-04

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Robert Alan May ,  Suddhasattwa Nad ,  Srinivas V. Pietambaram ,  Brandon C. Marin

IPC: H05K3/06 ,  H01L21/48 ,  H01L23/498 ,  H05K1/09

CPC classification number: H05K3/062 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894 ,  H05K1/09 ,  H05K3/067 ,  H01L25/0652

Abstract: Embodiments provides for a package substrate, including: a core comprising insulative material; first conductive traces in contact with a surface of the core; and buildup layers in contact with the first conductive traces and the surface of the core, the buildup layers comprising second conductive traces in an organic dielectric material. The first conductive traces comprise at least a first metal and a second metal, the first conductive traces comprise a first region proximate to and in contact with the core and a second region distant from the core, parallel and opposite to the first region, a relative concentration of the first metal to the second metal is higher in the first region than in the second region, and the relative concentration of the first metal to the second metal between the first region and the second region varies non-uniformly.

公开(公告)号：US20240112973A1

公开(公告)日：2024-04-04

申请号：US17958053

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Jeremy D. Ecton ,  Gang Duan ,  Brandon Christian Marin ,  Suddhasattwa Nad ,  Srinivas V. Pietambaram

IPC: H01L23/15 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L23/15 ,  H01L21/486 ,  H01L23/49827

Abstract: Through-glass vias (TGVs) are formed without the use of a planarization step to planarize the TGV fill material after filling holes that extend through a glass layer with the fill material. After the holes are filled with the fill material, the fill material is etched and the glass layer is etched. After etching of the glass is performed, the top and bottom surfaces of the glass layer are recessed relative to the top and bottom surfaces of the fill material in the holes, resulting in formation of fill material stubs. TGV pads are then formed on the fill material stubs. The resulting pads can have protrusions that extend away from a surface of the glass layer. If the TGVs are plated through-holes, a portion of the metal lining the inner wall of a TGV hole can extend past a surface of the glass layer and into a TGV pad.

公开(公告)号：US20240079334A1

公开(公告)日：2024-03-07

申请号：US17903856

申请日：2022-09-06

Applicant: Intel Corporation

Inventor： Jeremy D. Ecton ,  Brandon Christian Marin ,  Srinivas V. Pietambaram ,  Suddhasattwa Nad ,  Gang Duan

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/15 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/5381 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/15 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5386 ,  H01L25/0655 ,  H01L24/16

Abstract: A microelectronic structure, a semiconductor package including the structure, an IC device assembly including the structure, and a method of making the structure. The microelectronic structure includes: a first buildup layer and a second buildup layer including respective first and second electrically conductive structures; and a bridge layer including a glass material extending across a width thereof, the bridge layer between the first buildup layer and the second buildup layer and comprising: an interconnect bridge including third electrically conductive structures coupling a first set of the first electrically conductive structures to a second set of the first electrically conductive structures. Through glass vias (TGVs) extending from a top surface to a bottom surface of the bridge layer, the TGVs coupling a third set of the first electrically conductive structures to at least some of the second electrically conductive structures.