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公开(公告)号：US20190221423A1
公开(公告)日：2019-07-18
申请号：US15869258
申请日：2018-01-12
发明人： Ekmini A. De Silva , Nelson Felix , Jing Guo , Indira Seshadri
IPC分类号： H01L21/02 , H01L21/28 , H01L21/321 , H01L29/49 , G03F7/09
CPC分类号： H01L21/02074 , G03F7/091 , G03F7/094 , H01L21/28088 , H01L21/32115 , H01L29/0649 , H01L29/4966 , H01L29/7851
摘要： Embodiments of the present invention are directed to the wet stripping of an organic planarization layer (OPL) using reversible UV crosslinking and de-crosslinking. In a non-limiting embodiment of the invention, an interlayer dielectric is formed over a substrate. A trench is formed in the interlayer dielectric. A work function metal is formed over the interlayer dielectric such that a portion of the work function metal partially fills the trench. A UV sensitive OPL is formed over the work function metal such that a portion of the UV sensitive OPL fills the trench. The UV sensitive OPL can be crosslinked by applying light at a first UV frequency and de-crosslinked by applying light at a second UV frequency.
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公开(公告)号：US10354922B1
公开(公告)日：2019-07-16
申请号：US15855383
申请日：2017-12-27
IPC分类号： H01L21/324 , H01L21/8238 , H01L21/265 , H01L29/66 , H01L29/32 , H01L21/8234 , H01L21/266 , H01L21/311 , H01L21/3105 , H01L21/308 , H01L21/3065
摘要： Semiconductor devices and methods of forming the same include forming a wet-strippable hardmask over semiconductor fins. The wet-strippable hardmask is anisotropically etched away in a first device region. At least one semiconductor fin is doped in the first device region. The wet-strippable hardmask is isotropically etched away in a second device region. Semiconductor devices are formed from the fins in the first and second device regions.
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73.发明申请公开(公告)号：US20190214311A1
公开(公告)日：2019-07-11
申请号：US16241677
申请日：2019-01-07
发明人： Indira Seshadri , Ekmini Anuja De Silva , Jing Guo , Romain J. Lallement , Ruqiang Bao , Zhenxing Bi , Sivananda Kanakasabapathy
IPC分类号： H01L21/8238 , H01L21/28 , H01L27/092 , H01L21/308
CPC分类号： H01L21/823842 , H01L21/28185 , H01L21/3081 , H01L21/8221 , H01L21/823821 , H01L27/0688 , H01L27/0924 , H01L29/0673 , H01L29/42392 , H01L29/6653 , H01L29/66553 , H01L29/6681 , H01L29/7853
摘要： A semiconductor structure comprises a semiconductor substrate, an N-type stacked nanosheet channel structure formed on the semiconductor substrate, and a P-type stacked nanosheet channel structure formed adjacent to the N-type stacked nanosheet channel structure on the semiconductor substrate. Each of the adjacent N-type and P-type stacked nanosheet channel structures comprises a plurality of stacked channel regions with each such channel region being substantially surrounded by a gate dielectric layer and a gate work function metal layer, and with the gate work function metal layer being separated from the channel regions by the gate dielectric layer. The gate dielectric and gate work function metal layers of the adjacent N-type and P-type stacked nanosheet channel structures are substantially eliminated from a shared gate region between the adjacent N-type and P-type stacked nanosheet channel structures.
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74.发明申请公开(公告)号：US20190198398A1
公开(公告)日：2019-06-27
申请号：US15855383
申请日：2017-12-27
IPC分类号： H01L21/8234 , H01L21/266 , H01L21/311 , H01L21/3105 , H01L21/265 , H01L21/308
CPC分类号： H01L21/823431 , H01L21/26513 , H01L21/266 , H01L21/3065 , H01L21/3081 , H01L21/31058 , H01L21/31111 , H01L21/823418 , H01L21/823437 , H01L21/823475
摘要： Semiconductor devices and methods of forming the same include forming a wet-strippable hardmask over semiconductor fins. The wet-strippable hardmask is anisotropically etched away in a first device region. At least one semiconductor fin is doped in the first device region. The wet-strippable hardmask is isotropically etched away in a second device region. Semiconductor devices are formed from the fins in the first and second device regions.
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公开(公告)号：US20190189503A1
公开(公告)日：2019-06-20
申请号：US15847005
申请日：2017-12-19
发明人： Isabel Cristina Chu , Lawrence A. Clevenger , Leigh Anne H. Clevenger , Ekmini Anuja De Silva , Gauri Karve , Fee Li Lie , Nicole Adelle Saulnier , Indira Seshadri , Hosadurga Shobha
IPC分类号： H01L21/768 , H01L21/66 , H01L23/532 , H01L23/522
CPC分类号： H01L21/76837 , H01L21/76819 , H01L21/76877 , H01L22/14 , H01L23/5226 , H01L23/53228
摘要： Apparatus and methods for dielectric gap fill evaluations are provided. In one example, a method can comprise providing a gap fill substrate over one or more interlayer dielectric trenches of a dielectric layer and over a first material located in the one or more interlayer dielectric trenches. The method can also comprise depositing a gap fill candidate material within one or more gap fill substrate trenches of the gap fill substrate. Furthermore, the method can comprise etching the gap fill candidate material until a void within the first material is identified. Additionally, the method can comprise filling the one or more gap fill substrate trenches with a second material to form one or more contacts with the first material to measure a leakage current of one or more pitches.
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公开(公告)号：US10304744B1
公开(公告)日：2019-05-28
申请号：US15980427
申请日：2018-05-15
发明人： Praveen Joseph , Ekmini Anuja De Silva , Fee Li Lie , Stuart A. Sieg , Yann Mignot , Indira Seshadri
IPC分类号： H01L21/00 , H01L21/8234 , H01L21/027 , H01L21/311 , H01L29/66 , H01L21/02 , H01L27/088 , H01L29/78 , H01L29/10 , H01L21/306 , H01L21/308 , H01L21/762 , H01L21/033
摘要： Various methods and structures for fabricating a plurality of vertical fins in a vertical fin pattern on a semiconductor substrate where the vertical fins in the vertical fin pattern are separated by wide-open spaces, along a critical dimension, in a low duty cycle of 1:5 or lower. Adjacent vertical fins in the vertical fin pattern can be all separated by respective wide-open spaces, along a critical dimension, in a low duty cycle, and wherein pairs of adjacent vertical fins in the vertical fin pattern, along the critical dimension, are separated by a constant pitch value at near zero tolerance.
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公开(公告)号：US12107132B2
公开(公告)日：2024-10-01
申请号：US17491408
申请日：2021-09-30
发明人： Ruilong Xie , Indira Seshadri , Eric Miller , Kangguo Cheng
IPC分类号： H01L29/417 , H01L21/8234 , H01L23/528 , H01L27/088 , H01L27/092 , H01L29/40 , H01L29/423 , H01L29/786
CPC分类号： H01L29/41775 , H01L21/823475 , H01L23/5286 , H01L27/088 , H01L27/0922 , H01L29/401 , H01L29/41725 , H01L29/42392 , H01L29/78696
摘要： Embodiments disclosed herein include a semiconductor structure for reducing contact to contact shorting. The semiconductor structure may include a gate cut region with a liner and a dielectric core confined within a first lateral side of the liner and a second lateral side of the liner. The semiconductor structure may also include a first source/drain (S/D) contact overlapping the first lateral side and the dielectric core. The first S/D may include a line-end that contacts the second lateral side of the liner.
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78.发明公开公开(公告)号：US20240213243A1
公开(公告)日：2024-06-27
申请号：US18145003
申请日：2022-12-21
发明人： Shravana Kumar Katakam , Tao Li , Indira Seshadri , Ruilong Xie
IPC分类号： H01L27/092 , H01L23/50 , H01L23/522 , H01L29/08 , H01L29/66
CPC分类号： H01L27/092 , H01L23/50 , H01L23/5226 , H01L29/0847 , H01L29/66477
摘要： A microelectronic device includes a first source and drain structure adjacent to a second source and drain structure. A first conductive contact is in contact with a top surface and side surface of the first source and drain structure. A second conductive contact is in contact with a top surface and side surface of the second source and drain structure. The second conductive contact includes a via extension to connect to a backside component. A separating layer is located between the first conductive contact and the second conductive contact. A first sidewall of the separating layer is flush with the first conductive contact. A second sidewall of the separating layer is flush with the second conductive contact.
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公开(公告)号：US11990342B2
公开(公告)日：2024-05-21
申请号：US17481516
申请日：2021-09-22
CPC分类号： H01L21/28247 , H01L21/28158 , H01L29/517
摘要： The present disclosure relates to methods and apparatuses related to the deposition of a protective layer selective to an interlayer dielectric layer so that the protective layer is formed onto a top portion associated with the interlayer dielectric layer. In some embodiments, a method comprises: forming an interlayer dielectric layer on a substrate; covering a trench region with a metal liner, wherein the trench region is situated above the substrate and formed within the interlayer dielectric layer; and depositing a protective layer selective to the interlayer dielectric layer so that the protective layer is formed onto a top portion associated with the interlayer dielectric layer. In various embodiments, the depositing the protective layer comprises: repeatedly depositing the protective layer via a multi-deposition sequence; or depositing a self-assembled monolayer onto the top portion.
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公开(公告)号：US20230317802A1
公开(公告)日：2023-10-05
申请号：US17657006
申请日：2022-03-29
发明人： Junli Wang , Brent A Anderson , Terence Hook , Indira Seshadri , Albert M. Young , Stuart Sieg , Su Chen Fan , Shogo Mochizuki
IPC分类号： H01L29/417 , H01L29/40
CPC分类号： H01L29/41725 , H01L29/401
摘要： A high aspect ratio contact structure formed within a dielectric material includes a top portion and a bottom portion. The top portion of the contact structure includes a tapering profile towards the bottom portion. A first metal stack surrounded by an inner spacer is located within the top portion of the contact structure and a second metal stack is located within the bottom portion of the contact structure. A width of the bottom portion of the contact structure is greater than a minimum width of the top portion of the contact structure.
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