公开(公告)号：US20180096989A1

公开(公告)日：2018-04-05

申请号：US15498460

申请日：2017-04-26

Applicant: International Business Machines Corporation

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Bruce Miao ,  Xin Miao

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/06 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/78 ,  H01L21/311 ,  H01L21/02 ,  H01L21/027

CPC classification number: H01L27/088 ,  H01L21/0217 ,  H01L21/0274 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/823481 ,  H01L21/823487 ,  H01L29/0649 ,  H01L29/66666 ,  H01L29/7827

Abstract: A semiconductor device includes structures formed in first and second regions of a semiconductor substrate. The structures in the first region are spaced with a pitch P. The first and second regions are separated by an isolation region with spacing S, wherein S is greater than P. A first insulating layer is deposited and recessed to a target depth in the first region, and to a second depth in the isolation region. The second depth is lower than the target depth. A first etch stop layer is formed over the recessed first insulating layer, and a second insulating layer is formed over the first etch stop layer to increase a level of insulating material in the isolation region to the same target depth in the first device region. The recessed first insulating layer, first etch stop layer, and second insulating layer form a uniform thickness shallow trench isolation layer.

公开(公告)号：US09899515B1

公开(公告)日：2018-02-20

申请号：US15339072

申请日：2016-10-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Xin Miao ,  Wenyu Xu ,  Chen Zhang

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L21/8234 ,  H01L21/762 ,  H01L27/088 ,  H01L29/06 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L21/823814 ,  H01L21/76224 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823487 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/823885 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/41741 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/7827

Abstract: A method of fabricating a vertical fin field effect transistor with a merged top source/drain, including, forming a source/drain layer at the surface of a substrate, forming a plurality of vertical fins on the source/drain layer; forming protective spacers on each of the plurality of vertical fins, forming a sacrificial plug between two protective spacers, forming a filler layer on the protective spacers not in contact with the sacrificial plug, and selectively removing the sacrificial plug to form an isolation region trench between the two protective spacers.

公开(公告)号：US09859409B2

公开(公告)日：2018-01-02

申请号：US15140557

申请日：2016-04-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Xin Miao ,  Wenyu Xu ,  Chen Zhang

IPC: H01L21/20 ,  H01L29/76 ,  H01L29/66 ,  H01L21/306 ,  H01L29/12 ,  H01L21/3105 ,  H01L29/423 ,  H01L29/08

CPC classification number: H01L29/7613 ,  H01L29/0665 ,  H01L29/1033 ,  H01L29/127 ,  H01L29/42356 ,  H01L29/66439 ,  H01L29/66545

Abstract: Transistors and methods of forming the same include forming a fin having an active layer between two sacrificial layers. A dummy gate is formed over the fin. Spacers are formed around the dummy gate. The dummy gate is etched away to form a gap over the fin. Material from the two sacrificial layers is etched away in the gap. A gate stack is formed around the active layer in the gap. Source and drain regions are formed in contact with the active layer.

公开(公告)号：US09859389B1

公开(公告)日：2018-01-02

申请号：US15193404

申请日：2016-06-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Xin Miao ,  Wenyu Xu ,  Chen Zhang

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L29/78 ,  H01L29/417 ,  H01L21/311

CPC classification number: H01L29/41791 ,  H01L21/31116 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for forming a semiconductor device comprises forming a sacrificial gate stack on a substrate, spacers adjacent to the sacrificial gate stack, and a source/drain region on the substrate. A first insulator layer is formed on the source/drain region. A portion of the first insulator layer is removed to expose portions of the spacers. Exposed sidewall portions of the spacers are removed to reduce a thickness of the exposed portions of the spacers. A protective layer is deposited over the exposed sidewalls of the spacers and a second insulator layer is deposited over the protective layer. The sacrificial gate is removed to expose a channel region of the substrate. A gate stack is formed over the channel region of the substrate. Exposed portions of the first insulator layer and the second insulator layer are removed to expose the source/drain region, and a conductive is formed on the source/drain region.

公开(公告)号：US09859166B1

公开(公告)日：2018-01-02

申请号：US15413588

申请日：2017-01-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Xin Miao ,  Wenyu Xu ,  Chen Zhang

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L21/76 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/08 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/3105 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L29/51

CPC classification number: H01L21/823487 ,  H01L21/0217 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/32133 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823468 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7827

Abstract: A method is presented for forming a semiconductor structure. The method includes forming a plurality of fins over a source/drain region, forming a first spacer within troughs defined by the plurality of fins and depositing a high-k dielectric layer, a work function material layer, and a conducting layer. The method further includes etching the high-k dielectric layer, the work function material layer, and the conducting layer to form recesses between the plurality of fins, depositing a liner dielectric, and etching portions of the liner dielectric to form a plurality of second spacers having a U-shaped configuration. The method further includes forming an epitaxial layer over the plurality of fins such that a gap region is defined between the plurality of second spacers and the epitaxial layer.

公开(公告)号：US20170373162A1

公开(公告)日：2017-12-28

申请号：US15611388

申请日：2017-06-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Xin Miao ,  Wenyu Xu ,  Chen Zhang

IPC: H01L29/417 ,  H01L29/10 ,  H01L21/265 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L21/823431 ,  H01L21/845 ,  H01L29/0847 ,  H01L29/1041 ,  H01L29/41741 ,  H01L29/6656 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/7827 ,  H01L29/785 ,  H01L2029/7858

Abstract: A method of forming a vertical fin field effect transistor (vertical finFET) with an increased surface area between a source/drain contact and a doped region, including forming a doped region on a substrate, forming one or more interfacial features on the doped region, and forming a source/drain contact on at least a portion of the doped region, wherein the one or more interfacial features increases the surface area of the interface between the source/drain contact and the doped region compared to a flat source/drain contact-doped region interface.

公开(公告)号：US20170373159A1

公开(公告)日：2017-12-28

申请号：US15191566

申请日：2016-06-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Xin Miao ,  Wenyu Xu ,  Chen Zhang

IPC: H01L29/417 ,  H01L29/78 ,  H01L21/84 ,  H01L29/10 ,  H01L21/265 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/41791 ,  H01L21/26513 ,  H01L21/823431 ,  H01L21/845 ,  H01L29/1041 ,  H01L29/6656 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/7827 ,  H01L29/785 ,  H01L2029/7858

Abstract: A method of forming a vertical fin field effect transistor (vertical finFET) with an increased surface area between a source/drain contact and a doped region, including forming a doped region on a substrate, forming one or more interfacial features on the doped region, and forming a source/drain contact on at least a portion of the doped region, wherein the one or more interfacial features increases the surface area of the interface between the source/drain contact and the doped region compared to a flat source/drain contact-doped region interface.

公开(公告)号：US20170372956A1

公开(公告)日：2017-12-28

申请号：US15193831

申请日：2016-06-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Xin Miao ,  Wenyu Xu ,  Chen Zhang

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/28 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L21/76897 ,  H01L21/28114 ,  H01L21/28247 ,  H01L21/31116 ,  H01L21/76805 ,  H01L21/76808 ,  H01L21/76813 ,  H01L21/76831 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L29/42376 ,  H01L29/4983

Abstract: A semiconductor device includes a gate structure having a gate conductor and a sidewall spacer. A partial dielectric cap is formed on the gate conductor and extends less than a width of the gate conductor. A self-aligned contact is formed adjacent to the sidewall spacer of the gate structure and is electrically isolated from the gate conductor by the partial dielectric cap and the sidewall spacer.

公开(公告)号：US20170365596A1

公开(公告)日：2017-12-21

申请号：US15651503

申请日：2017-07-17

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Nicolas J. Loubet ,  Xin Miao ,  Alexander Reznicek

IPC: H01L27/02 ,  H01L29/161 ,  H01L29/06 ,  H01L21/324 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/16

CPC classification number: H01L27/0255 ,  H01L21/3247 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0629 ,  H01L27/0924 ,  H01L29/0638 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66537 ,  H01L29/785

Abstract: A semiconductor structure is provided that includes an electrostatic discharge (ESD) device integrated on the same semiconductor substrate as semiconductor fin field effect transistors (FinFETs). The ESD device includes a three-dimension (3D) wrap-around PN diode connected to the semiconductor substrate. The three-dimension (3D) wrap-around PN diode has an increased junction area and, in some applications, improved heat dissipation.

公开(公告)号：US20170323952A1

公开(公告)日：2017-11-09

申请号：US15356979

申请日：2016-11-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Ramachandra Divakaruni ,  Juntao LI ,  Xin Miao

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/6681 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7853

Abstract: Transistors include multiple stress liners. One or more channel structures are suspended at opposite ends from the plurality of stress liners. The stress liners provide a stress on the one or more channel structures. A gate is formed over and around the one or more channel structures, defining a channel region of the one or more channel structures that is covered by the gate. A source and drain region are formed on opposite sides of the gate.