公开(公告)号：US20070001734A1

公开(公告)日：2007-01-04

申请号：US11476040

申请日：2006-06-28

申请人： Masafumi Onouchi ,  Yusuke Kanno ,  Hiroyuki Mizuno ,  Yasuhisa Shimazaki ,  Tetsuya Yamada

发明人： Masafumi Onouchi ,  Yusuke Kanno ,  Hiroyuki Mizuno ,  Yasuhisa Shimazaki ,  Tetsuya Yamada

IPC分类号： H03K3/00

CPC分类号： H03K3/012 ,  H03K3/017 ,  H03K3/037

摘要： A low power consumption in a semiconductor integrated circuit device can be achieved by reducing a glitch power in a flip-flop. In a pulse-generator-incorporated auto-clock-gating flip-flop in which data latch is performed by using a pulsed clock, input data is latched based on an output of a dynamic XOR circuit, which is a comparator circuit, during a period when the pulsed clock is at a high level, and the dynamic XOR circuit is cut off during a period when the pulsed clock is at a low level.

摘要翻译： 可以通过减少触发器中的毛刺功率来实现半导体集成电路器件中的低功耗。 在其中通过使用脉冲时钟执行数据锁存的内置脉冲发生器的自动时钟门控触发器中，在一段时间内基于作为比较器电路的动态异或电路的输出来锁存输入数据 当脉冲时钟处于高电平时，并且在脉冲时钟处于低电平的时段期间动态异或电路被切断。

公开(公告)号：US07112999B2

公开(公告)日：2006-09-26

申请号：US11124060

申请日：2005-05-09

申请人： Hiroyuki Mizuno ,  Masataka Minami ,  Koichiro Ishibashi ,  Masayuki Miyazaki

发明人： Hiroyuki Mizuno ,  Masataka Minami ,  Koichiro Ishibashi ,  Masayuki Miyazaki

IPC分类号： H03K3/01

CPC分类号： H01L27/0207 ,  H01L27/092 ,  H01L27/105 ,  H03K3/011 ,  H03K3/0315 ,  H03K19/0016

摘要： A semiconductor integrated circuit device comprising a logical circuit including a MIS transistor formed on a semiconductor substrate, a control circuit for controlling a threshold voltage of the MIS transistor forming the logical circuit, an oscillation circuit including a MIS transistor formed on the semiconductor substrate, the oscillation circuit being constructed so that the frequency of an oscillation output thereof can be made variable, and a buffer circuit, in which the control circuit is supplied with a clock signal having a predetermined frequency and the oscillation output of the oscillation circuit so that the control circuit compares the frequency of the oscillation output and the frequency of the clock signal to output a first control signal, the oscillation circuit is controlled by the first control signal so that the frequency of the oscillation output corresponds to the frequency of the clock signal, the control of the frequency of the oscillation output being performed in such a manner that the first control signal controls a threshold voltage of the MIS transistor forming the oscillation circuit, and the buffer circuit is constructed so that it is inputted with the first control signal to output a second control signal corresponding to the first control signal, the second control signal controlling the threshold voltage of the MIS transistor forming the logical circuit.

公开(公告)号：US07106123B2

公开(公告)日：2006-09-12

申请号：US11117479

申请日：2005-04-29

申请人： Yusuke Kanno ,  Hiroyuki Mizuno ,  Takeshi Sakata ,  Takao Watanabe

发明人： Yusuke Kanno ,  Hiroyuki Mizuno ,  Takeshi Sakata ,  Takao Watanabe

IPC分类号： H03L5/00

CPC分类号： H03K19/0016 ,  H03K19/018521

摘要： A semiconductor device including a level converter (LSC) is disclosed. The level converter comprises a voltage-up circuit (LSC1) that operates on low voltage of power supply (VDD) and steps up voltage enough to drive the level converter and a level converter circuit (LSC2) that operates on high voltage of power supply (VDDQ). The voltage-up circuit is capable of constantly generating 2×VDD so that the level converter can convert a low voltage of power supply (VDD) below 1 V to VDDQ. This voltage-up circuit can be configured only with MOSFET transistors produced by thin oxide film deposition, thus enabling high-speed operation. To facilitate designing a circuit for preventing a leakage current from occurring in the level converter during sleep mode of a low-voltage-driven circuit (CB1), the level converter circuit (LSC2) includes a leak protection circuit (LPC) that exerts autonomous control for leak prevention, dispensing with external control signals.

摘要翻译： 公开了一种包括电平转换器（LSC）的半导体器件。 电平转换器包括在低电压（VDD）下工作并升压足以驱动电平转换器的升压电路（LSC 1）和在高电压功率下工作的电平转换器电路（LSC 2） 电源（VDDQ）。 升压电路能够持续产生2xVDD，因此电平转换器可将低于1 V的低电压电压（VDD）转换为VDDQ。 该升压电路只能由通过薄氧化膜沉积制造的MOSFET晶体管配置，从而实现高速操作。 为了便于设计用于防止低电压驱动电路（CB 1）的睡眠模式期间在电平转换器中发生漏电流的电路，电平转换器电路（LSC 2）包括泄漏保护电路（LPC） 自动控制防泄漏，外接控制信号。

公开(公告)号：US20060146623A1

公开(公告)日：2006-07-06

申请号：US11363085

申请日：2006-02-28

申请人： Hiroyuki Mizuno ,  Takeshi Sakata ,  Nobuhiro Oodaira ,  Takao Watanabe ,  Yusuke Kanno

发明人： Hiroyuki Mizuno ,  Takeshi Sakata ,  Nobuhiro Oodaira ,  Takao Watanabe ,  Yusuke Kanno

IPC分类号： G11C7/00

CPC分类号： G11C11/4076 ,  G11C7/04 ,  G11C7/065 ,  G11C7/08 ,  G11C7/12 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  G11C2207/002 ,  G11C2207/005

摘要： The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large extent for fluctuation of processes. The present invention provides the following typical effects. A switch means is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. The VDL is the maximum amplitude voltage of the bit line BL. A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data. When the bit line BL and local bit line LBL are capacitance-coupled via a capacitor, it is recommended to use a latch type sense amplifier SA connected to the local bit line LBL.

摘要翻译： 本发明提供了一种用于DRAM存储单元的感测电路，以覆盖当电源电压降低时感测时间变得显着更长的事件，当温度升高时，低电压条件下的感测时间变短，感测时间变为 过程波动很大程度。 本发明提供以下典型的效果。 在位线BL和连接到存储器单元的局部位线LBL之间提供开关装置以隔离和耦合这些位线。位线BL被预充电到VDL / 2的电压，而局部位线LBL被预充电 到VDL的电压。 VDL是位线BL的最大幅度电压。 读出放大器SA包括第一电路，其包括具有连接到位线BL的栅极的差分MOS对，以及连接到用于全幅放大的局部位线LBL并用于保持该数据的第二电路。 当位线BL和本地位线LBL通过电容器电容耦合时，建议使用连接到局部位线LBL的锁存型读出放大器SA。

公开(公告)号：US20060097191A1

公开(公告)日：2006-05-11

申请号：US11260254

申请日：2005-10-28

申请人： Hiroyuki Mizuno

发明人： Hiroyuki Mizuno

IPC分类号： A61N5/00

CPC分类号： H01J37/3026 ,  B82Y10/00 ,  B82Y40/00 ,  G03F1/20 ,  H01J37/3174 ,  H01J2237/31776

摘要： An electron beam control method has the following steps, selecting one of a plurality of pattern openings by a character beam electrode having a plurality of electrode units to allow an electron beam to pass through any pattern opening on an aperture mask on which the plurality of pattern openings are formed, determining whether or not a synchronization error of deflected operation of the electron beam performed by the plurality of electrode units is equal to or less than a tolerance, determining whether or not the electron beam is irradiated with a sample by selecting the pattern openings in sequence by the character beam electrode in a state of controlling a path of the electron beam by a blanking electrode not to irradiate the sample with the electron beam, when determined that the synchronization error is equal to or less than the tolerance, and decreasing the tolerance when determined that the electron beam is irradiated with the sample.

摘要翻译： 电子束控制方法具有以下步骤：通过具有多个电极单元的字符电极来选择多个图形开口中的一个，以允许电子束通过孔径掩模上的多个图案 形成开口，确定多个电极单元执行的电子束的偏转操作的同步误差是否等于或小于公差，通过选择图案来确定电子束是否被照射样品 当确定同步误差等于或小于公差时，通过字符光束电极在由控制不用电子束照射样品的消隐电极的电子束的路径的状态下依次进行开口，并且减小 当确定电子束被照射样品时的公差。

公开(公告)号：US06987415B2

公开(公告)日：2006-01-17

申请号：US10765923

申请日：2004-01-29

申请人： Hiroyuki Mizuno ,  Koichiro Ishibashi ,  Takanori Shimura ,  Toshihiro Hattori

发明人： Hiroyuki Mizuno ,  Koichiro Ishibashi ,  Takanori Shimura ,  Toshihiro Hattori

IPC分类号： H03K3/01

CPC分类号： H01L27/0207 ,  G11C5/14 ,  G11C5/146 ,  G11C5/147 ,  H01L27/0928 ,  H01L27/11807 ,  H01L2924/0002 ,  H03K19/0016 ,  H01L2924/00

摘要： In order to provide a semiconductor IC unit such as a microprocessor, etc., which satisfies both fast operation and lower power consumption properties with its high quality kept, the semiconductor IC unit of the present invention is composed so as to include a main circuit (LOG) provided with transistors, which is formed on a semiconductor substrate, and a substrate bias controlling circuit (VBC) used for controlling a voltage to be applied to the substrate, and the main circuit includes switching transistors (MN1 and MP1) used for controlling a voltage to be applied to the substrate and control signals output from the substrate bias controlling circuit is entered to the gate of each of the switching transistors and the control signal is returned to the substrate bias controlling circuit.

摘要翻译： 为了提供满足快速操作和低功耗特性的诸如微处理器等的半导体IC单元，保持其高质量，本发明的半导体IC单元被构成为包括主电路（ LOG），其形成在半导体衬底上的晶体管和用于控制施加到衬底的电压的衬底偏置控制电路（VBC），并且主电路包括使用的开关晶体管（MN 1和MP 1） 用于控制施加到衬底的电压，并且从衬底偏置控制电路输出的控制信号被输入到每个开关晶体管的栅极，并且控制信号返回到衬底偏置控制电路。

公开(公告)号：US06970036B2

公开(公告)日：2005-11-29

申请号：US10860011

申请日：2004-06-04

申请人： Hiroyuki Mizuno

发明人： Hiroyuki Mizuno

IPC分类号： H01L21/822 ,  G06F1/26 ,  G06F1/32 ,  H01L27/04 ,  H03K19/00 ,  H03K19/096 ,  G05F1/10

CPC分类号： G06F1/324 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3296 ,  H03K19/0016 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D50/20 ,  Y10T307/25 ,  Y10T307/406

摘要： A semiconductor integrated circuit device for fast and low power operations, comprising a plurality of circuit blocks of a chip, each of which has a plurality of states with different power consumption values. A power management circuit determines the state of each of the circuit blocks so as not to exceed a maximum power consumption value of the semiconductor integrated circuit device by considering the power consumption of each circuit block and by each state transition in each circuit block. The maximum power consumption value may be preset or adjustable after fabrication.

摘要翻译： 一种用于快速和低功率操作的半导体集成电路器件，包括芯片的多个电路块，每个电路块具有不同功耗值的多个状态。 功率管理电路通过考虑每个电路块的功耗和每个电路块中的每个状态转换来确定每个电路块的状态，以便不超过半导体集成电路器件的最大功耗值。 最大功耗值可以在制造后预设或调节。

公开(公告)号：US06940739B2

公开(公告)日：2005-09-06

申请号：US10307954

申请日：2002-12-03

申请人： Hiroyuki Mizuno ,  Suguru Tachibana ,  Koichiro Ishibashi ,  Kenichi Osada

发明人： Hiroyuki Mizuno ,  Suguru Tachibana ,  Koichiro Ishibashi ,  Kenichi Osada

IPC分类号： G11C11/41 ,  G06F12/08 ,  G11C5/06 ,  G11C7/06 ,  G11C7/18 ,  G11C7/22 ,  G11C11/401 ,  G11C11/409

CPC分类号： G11C7/18 ,  G06F12/0893 ,  G11C5/063 ,  G11C7/06 ,  G11C7/22 ,  G11C2207/108 ,  Y02D10/13

摘要： A memory structure/circuit has at least two memory cell arrays connected to each other in a hierarchy. The bit lines of the two or more memory cell arrays are connected by hierarchy switches. The memory cells of one of the arrays can be read out faster than the others by using the hierarchy switches to select one array without selecting the other arrays. So the data that is read with higher frequency can be selectively read out faster if it is stored in the faster access memory array. If the data in the faster access memory cell array includes a copy of the data in the other array, it can be used as a cache memory. A tag array and data array in combination that are connected to another tag array and data array in combination through hierarchy switch connections can provide a cache memory that is direct mapped or set associative, and also full associative. The memory device can be used in a semiconductor data processor having a CPU in which the memory device is connected to the CPU through a bus, wherein both the CPU and the memory device are formed on a single semiconductor substrate. The memory device can also be an off-chip device.

摘要翻译： 存储器结构/电路具有至少两个相互连接的存储单元阵列。 两个或多个存储单元阵列的位线通过分层开关连接。 通过使用层次结构开关选择一个阵列而不选择其他阵列，其中一个阵列的存储单元可以比其他阵列更快地读出。 因此，如果存储在更快的访问存储器阵列中，则可以更快地选择性地读出更高频率读取的数据。 如果快速访问存储单元阵列中的数据包含另一阵列中的数据副本，则可以将其用作高速缓冲存储器。 组合的标签阵列和数据阵列通过分层交换机连接组合连接到另一标签阵列和数据阵列，可以提供直接映射或设置关联的高速缓存存储器，也可以是完全关联的。 存储器件可用于具有CPU的半导体数据处理器，其中存储器件通过总线连接到CPU，其中CPU和存储器件均形成在单个半导体衬底上。 存储器件也可以是片外器件。

公开(公告)号：US06922113B2

公开(公告)日：2005-07-26

申请号：US10718608

申请日：2003-11-24

申请人： Hiroyuki Mizuno ,  Hirokazu Aoki ,  Koichiro Ishibashi

发明人： Hiroyuki Mizuno ,  Hirokazu Aoki ,  Koichiro Ishibashi

IPC分类号： G06F1/08 ,  G06F1/10 ,  H03K3/0231 ,  H03K3/03 ,  H03L7/00 ,  H03L7/081 ,  H03L7/089 ,  H03L7/099 ,  H03L7/18 ,  H03B27/00

CPC分类号： H03L7/0805 ,  G06F1/10 ,  H03K3/0231 ,  H03K3/03 ,  H03K3/0322 ,  H03L7/00 ,  H03L7/0812 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/18

摘要： The oscillation circuit includes at least two ring oscillation circuits in each of which a plurality of inverters are connected in a ring shape in a multi-stage fashion, and a conductive wiring line. The output of at least one inverter of each of the ring oscillation circuits is connected to the conductive wiring line, whereby the plurality of ring oscillators are caused to oscillate at an identical frequency. A PLL is constructed in such a way that the oscillation circuit obtained by the above means is formed into a voltage-controlled oscillation circuit, and that a phase-frequency comparator, a charge pump circuit and a low-pass filter are employed.

摘要翻译： 振荡电路包括至少两个环形振荡电路，其中多个反相器以多级方式连接成环状，并且具有导电布线。 每个环形振荡电路的至少一个反相器的输出端连接到导电布线，从而使多个环形振荡器以相同的频率振荡。 PLL被构造成使得通过上述装置获得的振荡电路形成为压控振荡电路，并且采用相位 - 频率比较器，电荷泵电路和低通滤波器。

公开(公告)号：US20050104133A1

公开(公告)日：2005-05-19

申请号：US10921854

申请日：2004-08-20

申请人： Yusuke Kanno ,  Hiroyuki Mizuno ,  Naohiko Irie

发明人： Yusuke Kanno ,  Hiroyuki Mizuno ,  Naohiko Irie

IPC分类号： H01L21/822 ,  G11C5/06 ,  G11C11/417 ,  H01L21/82 ,  H01L27/02 ,  H01L27/04 ,  H01L27/092 ,  H01L27/118 ,  H03K3/037 ,  H03K3/356 ,  H03K3/3562 ,  H03K19/00 ,  H03K19/0175 ,  H03K19/08 ,  H01L29/76 ,  G11C11/24

CPC分类号： G01R31/318572 ,  G11C5/063 ,  G11C11/417 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/11807 ,  H01L2924/0002 ,  H03K3/356008 ,  H03K3/35625 ,  H03K19/0016 ,  H01L2924/00

摘要： In a low power consumption mode in which prior data is retained upon power shutdown, the return speed thereof is increased. While use of an existent data retaining flip-flop may be considered, this is not preferred since it increases area overhead such as enlargement of the size of a cell. A power line for data retention for power shutdown is formed with wirings finer than a usual main power line. Preferably, power lines for a data retention circuit are considered as signal lines and wired by automatic placing and mounting. For this purpose, terminals for the power line for data retention are previously designed by providing the terminals therefor for the cell in the same manner as in the existent signal lines. Additional layout for power lines is no longer necessary for the cell, which enables a decrease in the area and design by an existent placing and routing tool.

摘要翻译： 在功率关闭时保留先前数据的低功耗模式下，其返回速度增加。 虽然可以考虑使用现有的数据保持触发器，但是这不是优选的，因为它增加了诸如扩大单元大小的面积开销。 用于电源关闭的数据保持的电源线由比通常的主电源线更细的布线形成。 优选地，用于数据保持电路的电力线被认为是信号线，并通过自动放置和安装进行布线。 为此，先前通过以与现有信号线相同的方式为小区提供终端来设计用于数据保持的电力线的终端。 电池线的附加布局不再需要，这使得现有的放置和布线工具能够减少面积和设计。