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225 条记录 (耗时 0.042 秒)

    Signal transition detector circuit
    72.
    发明授权
    Signal transition detector circuit 失效
    信号转换检测电路

    公开(公告)号：US5680066A

    公开(公告)日：1997-10-21

    申请号：US182699

    申请日：1994-01-13

    申请人： Takashi Akioka ,  Masahiro Iwamura ,  Atsushi Hiraishi ,  Yuji Yokoyama ,  Nozomu Matsuzaki ,  Tatsumi Yamauchi ,  Yutaka Kobayashi ,  Nobuyuki Gotou ,  Akira Ide ,  Masahiro Yamamura ,  Hideaki Uchida

    发明人： Takashi Akioka ,  Masahiro Iwamura ,  Atsushi Hiraishi ,  Yuji Yokoyama ,  Nozomu Matsuzaki ,  Tatsumi Yamauchi ,  Yutaka Kobayashi ,  Nobuyuki Gotou ,  Akira Ide ,  Masahiro Yamamura ,  Hideaki Uchida

    IPC分类号： G11C7/10 ,  G11C8/06 ,  G11C8/10 ,  G11C8/18 ,  H03K5/1534 ,  H03K19/0175 ,  H03K5/153 ,  G01R29/02 ,  H03K3/033

    CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C8/06 ,  G11C8/10 ,  G11C8/18 ,  H03K19/017518 ,  H03K5/1534

    摘要： A semiconductor device which includes at least one of (1) an input buffer circuit formed of an input level converter and a non-inverting buffer circuit and an inverting buffer circuit each including BiCMOS circuitry which effects high-speed operation; (2) a decoder circuit formed of plural logic gates each of which is composed of the combination of MOS and bipolar circuitry; (3) a sense amplifier circuit including a multiemitter transistor; (4) a signal or address transition detector circuit which includes input circuits each receiving, for example, an address signal of a voltage amplitude and outputting a current amplitude signal in response to a change in level of the address signal, and a detector circuit connected thereto which has a cascode amplifier arranged such that it receives current amplitude signals at an input thereof and in which the cascode amplifier input is maintained at a substantially constant voltage, in which the detection circuit detects a transition of one or more of the current amplitude signals and, in response thereto, generates an ATD signal of a voltage amplitude; and (5) an output buffer circuit, in which the decoder, sense amplifier and output buffer of the device such as for a memory are controlled in accordance with signals from a clock generator, which is responsive to the ATD signal.

    摘要翻译： 一种半导体器件，其包括以下中的至少一个：（1）由输入电平转换器和非反相缓冲电路构成的输入缓冲电路和各自包括实现高速操作的BiCMOS电路的反相缓冲电路; （2）由多个逻辑门形成的解码器电路，每个逻辑门由MOS和双极电路的组合组成; （3）包括多端子晶体管的读出放大器电路; （4）信号或地址转换检测器电路，其包括各自接收例如电压幅度的地址信号并且响应于地址信号的电平的变化而输出当前振幅信号的输入电路，以及连接的检测器电路 具有共源共栅放大器，其布置成使得其在其输入处接收电流幅度信号，并且其中共源共栅放大器输入保持在基本上恒定的电压，其中检测电路检测到一个或多个当前幅度信号的转变 并且响应于此产生电压幅度的ATD信号; 以及（5）输出缓冲器电路，其中根据来自响应于ATD信号的时钟发生器的信号来控制诸如存储器的装置的解码器，读出放大器和输出缓冲器。

    Semiconductor memory device and method of operation thereof
    73.
    发明授权
    Semiconductor memory device and method of operation thereof 失效
    半导体存储器件及其操作方法

    公开(公告)号：US5629888A

    公开(公告)日：1997-05-13

    申请号：US182503

    申请日：1994-01-18

    申请人： Ryuichi Saito ,  Hidekatsu Onose ,  Yutaka Kobayashi ,  Michio Ohue

    发明人： Ryuichi Saito ,  Hidekatsu Onose ,  Yutaka Kobayashi ,  Michio Ohue

    IPC分类号： G11C14/00 ,  G11C11/22 ,  G11C11/56 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/108 ,  H01L27/112 ,  H01L27/115

    CPC分类号： H01L27/11502 ,  G11C11/22 ,  G11C11/5657 ,  G11C16/08 ,  G11C8/14 ,  H01L27/10805

    摘要： A semiconductor memory device has a plurality of memory cells in an array, into which the memory cells data is writable, and which can subsequently be read. Each memory cell has a switching element with one terminal connected to a bit line of the array another terminal connected to at least one ferroelectric capacitor, and a control terminal connected to a word line. The cell may then be operated to detect the change in polarization of the ferroelectric capacitor when a voltage is applied which is not sufficient to cause a change of state of the ferroelectric capacitor. Alternatively, a ferroelectric capacitor and a capacitor other than a ferroelectric capacitor is connected to the switching element. In a further alternative, a plurality of ferroelectric capacitors are connected to the switching element, so that different data are writable into each.

    摘要翻译： 半导体存储器件具有阵列中的多个存储器单元，存储器单元数据可写入其中，并且随后可以读取存储单元。 每个存储单元具有开关元件，一个端子连接到阵列的位线，另一个端子连接到至少一个铁电电容器，以及控制端子连接到字线。 然后可以操作电池以在施加电压时检测铁电电容器的极化变化，这不足以引起铁电电容器的状态改变。 或者，铁电电容器和除铁电电容器之外的电容器连接到开关元件。 在另一替代方案中，多个铁电电容器连接到开关元件，使得不同的数据可写入每个。

    Semiconductor integrated circuit having logic gates
    76.
    发明授权
    Semiconductor integrated circuit having logic gates 失效
    具有逻辑门的半导体集成电路

    公开(公告)号：US5387827A

    公开(公告)日：1995-02-07

    申请号：US643372

    申请日：1991-01-22

    申请人： Yuji Yokoyama ,  Takashi Akioka ,  Masahiro Iwamura ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Tatsumi Yamauchi ,  Shigeru Takahashi ,  Nobuyuki Gotou ,  Akira Ide

    发明人： Yuji Yokoyama ,  Takashi Akioka ,  Masahiro Iwamura ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Tatsumi Yamauchi ,  Shigeru Takahashi ,  Nobuyuki Gotou ,  Akira Ide

    IPC分类号： G11C7/10 ,  G11C8/10 ,  H03K19/0948 ,  H03K19/23

    CPC分类号： H03K19/0948 ,  G11C7/1051 ,  G11C7/1078 ,  G11C8/10

    摘要： A semiconductor integrated logic circuit is provided which includes a plurality of logic gates each having a first input terminal for respectively receiving first input signals, wherein each of the logic gates is coupled to a common node. In one embodiment, first and second switching elements are also coupled to the common node. The first and second switching elements are both coupled to a second input terminal for receiving a second input signal which is common to the plurality of logic gates, and both operate complementary to one another in response to the second input signal. This arrangement is particularly effective for decoders in semiconductor memory circuits which use a common NMOS to receive one input for a plurality of logic decoder gates. An improved read/write arrangement is also provided for semiconductor memory circuits which includes circuitry to prevent connection of a common read line to the data lines during the writing operation. This enhances the writing speed by removing the load of the common read line during writing.

    摘要翻译： 提供了一种半导体集成逻辑电路，其包括多个逻辑门，每个逻辑门具有用于分别接收第一输入信号的第一输入端，其中每个逻辑门耦合到公共节点。 在一个实施例中，第一和第二开关元件也耦合到公共节点。 第一和第二开关元件都耦合到第二输入端子，用于接收多个逻辑门公共的第二输入信号，并且它们都响应于第二输入信号互相互补。 这种布置对于使用公共NMOS来接收多个逻辑解码器门的一个输入的半导体存储器电路中的解码器特别有效。 还提供了一种用于半导体存储器电路的改进的读/写布置，其包括在写入操作期间防止公共读取线连接到数据线的电路。 这通过在写入期间去除公共读取线的负载来增强写入速度。

    Semiconductor memory device having bipolar transistor and structure to avoid soft error
    78.
    发明授权
    Semiconductor memory device having bipolar transistor and structure to avoid soft error 失效
    半导体存储器件具有双极晶体管和结构，以避免软错误

    公开(公告)号：US5324982A

    公开(公告)日：1994-06-28

    申请号：US769680

    申请日：1991-10-02

    申请人： Shinji Nakazato ,  Hideaki Uchida ,  Yoshikazu Saito ,  Masahiro Yamamura ,  Yutaka Kobayashi ,  Takahide Ikeda ,  Ryoichi Hori ,  Goro Kitsukawa ,  Kiyoo Itoh ,  Nobuo Tanba ,  Takao Watanabe ,  Katsuhiro Shimohigashi ,  Noriyuki Homma

    发明人： Shinji Nakazato ,  Hideaki Uchida ,  Yoshikazu Saito ,  Masahiro Yamamura ,  Yutaka Kobayashi ,  Takahide Ikeda ,  Ryoichi Hori ,  Goro Kitsukawa ,  Kiyoo Itoh ,  Nobuo Tanba ,  Takao Watanabe ,  Katsuhiro Shimohigashi ,  Noriyuki Homma

    IPC分类号： H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/105 ,  H01L27/108 ,  H01L27/04 ,  H01L29/70

    CPC分类号： H01L27/10805 ,  H01L27/0214 ,  H01L27/0623 ,  H01L27/0922 ,  H01L27/0218 ,  H01L27/105 ,  Y10S257/901 ,  Y10S257/904

    摘要： Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements. As a second aspect of the present invention, first carrier absorbing areas (to absorb minority carriers) are located between the memory array and the switching circuit of the peripheral circuit, and second carrier absorbing areas are provided to surround input protective elements of the device. As a third embodiment of the present invention, a plurality of isolation regions of the same conductivity type are provided, with unequal voltages applied to these isolation regions, or unequal voltages applied to the substrate, on the one hand, and to these isolation regions, on the other.

    摘要翻译： 公开了一种半导体器件，例如半导体存储器件，其结构可以避免少数载流子从半导体衬底侵入形成在衬底上的器件的部件。 半导体存储器件例如可以是SRAM或DRAM，并且在衬底上包括存储器阵列和外围电路。 在本发明的一个方面中，在外围电路和存储器阵列中的至少一个之下提供与衬底相同的导电类型但具有比衬底的杂质浓度更高的杂质浓度的掩埋层。 另外的区域可以例如从掩埋层延伸到半导体衬底的表面，掩埋层和组合的另外的区域用作屏蔽以防止少数载流子穿透到器件元件。 作为本发明的第二方面，第一载流子吸收区域（以吸收少数载流子）位于存储器阵列和外围电路的开关电路之间，并且第二载流子吸收区域被设置为环绕该器件的输入保护元件。 作为本发明的第三实施例，提供了相同导电类型的多个隔离区域，一方面施加到这些隔离区域的不同电压或施加到基板的不同电压以及这些隔离区域， 在另一。