Patent search ap:("TEXAS INSTRUMENTS INCORPORATED") AND inv:"Archana Venugopal" Page 8

71.

发明申请
Integration of graphene and boron nitrite hetero-structure device over semiconductor layer 审中-公开

公开(公告)号：US20190288122A1

公开(公告)日：2019-09-19

申请号：US16501731

申请日：2019-05-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Archana Venugopal , Luigi Colombo , Arup Polley

IPC: H01L29/786 , H01L29/16 , H01L21/02 , H01L29/20 , H01L29/267 , H01L27/092 , H01L21/8258 , H01L29/66 , H01L29/45 , H01L29/49

Abstract: A microelectronic device includes a gated graphene component over a semiconductor material. The gated graphene component includes a graphitic layer having at least one layer of graphene. The graphitic layer has a channel region, a first connection and a second connection make electrical connections to the graphitic layer adjacent to the channel region. The graphitic layer is isolated from the semiconductor material. A backgate region having a first conductivity type is disposed in the semiconductor material under the channel region. A first contact field region and a second contact field region are disposed in the semiconductor material under the first connection and the second connection, respectively. At least one of the first contact field region and the second contact field region has a second, opposite, conductivity type. A method of forming the gated graphene component in the microelectronic device with a transistor is disclosed.

72.

发明申请
INTERCONNECT VIA WITH GROWN GRAPHITIC MATERIAL 审中-公开

公开(公告)号：US20190229051A1

公开(公告)日：2019-07-25

申请号：US16372455

申请日：2019-04-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Archana Venugopal , Benjamin Stassen Cook , Luigi Colombo , Robert Reid Doering

IPC: H01L23/528 , H01L21/768 , H01L23/367 , H01L21/285 , H01L21/288 , H01L21/3205 , H01L23/48 , H01L23/31 , H01L23/522 , H01L23/532 , H01L21/324 , H01L21/3105 , H01L23/373

CPC classification number: H01L23/528 , H01L21/28556 , H01L21/28562 , H01L21/288 , H01L21/31051 , H01L21/32051 , H01L21/32055 , H01L21/324 , H01L21/76802 , H01L21/76834 , H01L21/76876 , H01L21/76879 , H01L21/76885 , H01L21/76895 , H01L23/3107 , H01L23/3677 , H01L23/373 , H01L23/481 , H01L23/5226 , H01L23/5227 , H01L23/53209 , H01L23/53276 , H01L2224/48463

Abstract: An integrated circuit has a substrate and an interconnect region disposed on the substrate. The interconnect region includes a plurality of interconnect levels. Each interconnect level includes interconnects in dielectric material. The integrated circuit includes a graphitic via in the interconnect region. The graphitic via vertically connects a first interconnect in a first interconnect level to a second interconnect in a second, higher, interconnect level. The graphitic via includes a cohered nanoparticle film of nanoparticles in which adjacent nanoparticles cohere to each other, and a layer of graphitic material disposed on the cohered nanoparticle film. The nanoparticles include one or more metals suitable for catalysis of the graphitic material. The cohered nanoparticle film is formed by a method which includes an additive process. The graphitic via is electrically coupled to an active component of the integrated circuit.

73.

发明申请
STRUCTURE TO ENABLE HIGHER CURRENT DENSITY IN INTEGRATED CIRCUIT RESISTOR 审中-公开

公开(公告)号：US20190139861A1

公开(公告)日：2019-05-09

申请号：US15807370

申请日：2017-11-08

Applicant: Texas Instruments Incorporated

Inventor： Dhishan Kande , Archana Venugopal

IPC: H01L23/42 , H01L49/02

CPC classification number: H01L23/42 , H01L21/768 , H01L23/485 , H01L23/5228 , H01L28/20

Abstract: An integrated circuit has a substrate including semiconductor material and a resistor in an interconnect region, above a first level of interconnect lines. The integrated circuit further includes an electrically isolated thermal conduit having one or more interconnect lines in every interconnect level lower than the resistor. The interconnect lines of the thermal conduit are directly connected through one or more vertical interconnects, including contacts, and possibly vias, to a gate structure located on a dielectric material over the semiconductor material of the substrate. The thermal conduit is electrically isolated from the resistor, from all active components in the integrated circuit, and from the semiconductor material of the substrate.

74.

发明授权
Fusible link cell with dual bit storage 有权

公开(公告)号：US10153053B2

公开(公告)日：2018-12-11

申请号：US15787905

申请日：2017-10-19

Applicant: Texas Instruments Incorporated

Inventor： Sunil Kumar Dusa , Richard Allen Bailey , Archana Venugopal , John Anthony Rodriguez , Michael Allen Ball

IPC: G11C17/18 , G11C17/16

Abstract: A fuse-programmable register or memory location having a plurality of fusible links of differing electrical characteristics in parallel. In one embodiment, three fusible links with different resistances are provided, such that application of a programming voltage non-uniformly distributes the current among the links, allowing varying voltages to selectively blow one or more of the links. Sensing of the programmed state is performed by applying a voltage across the parallel links and measuring the current in comparison with a plurality of reference currents. Reduction in the overhead chip area per bit and in the serial data communication latency are obtained.

75.

发明申请
HIGH THERMAL CONDUCTIVITY VIAS BY ADDITIVE PROCESSING 审中-公开

公开(公告)号：US20180151471A1

公开(公告)日：2018-05-31

申请号：US15361399

申请日：2016-11-26

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook , Archana Venugopal , Luigi Colombo , Robert Reid Doering

IPC: H01L23/367 , H01L23/522 , H01L23/373 , H01L23/00 , H01L21/768 , H01L21/48

CPC classification number: H01L23/3677 , H01L21/4882 , H01L23/3731 , H01L23/3733 , H01L23/3736

Abstract: An integrated circuit has a substrate and an interconnect region disposed on the substrate. The interconnect region includes a plurality of interconnect levels. Each interconnect level includes interconnects in dielectric material. The integrated circuit includes a thermal via in the interconnect region. The thermal via extends vertically in at least one of the interconnect levels in the interconnect region. The thermal via includes a cohered nanoparticle film in which adjacent nanoparticles are cohered to each other. The thermal via has a thermal conductivity higher than dielectric material touching the thermal via. The cohered nanoparticle film is formed by a method which includes an additive process.

76.

发明申请
FUSIBLE LINK CELL WITH DUAL BIT STORAGE 审中-公开

公开(公告)号：US20180040381A1

公开(公告)日：2018-02-08

申请号：US15787905

申请日：2017-10-19

Applicant: Texas Instruments Incorporated

Inventor： Sunil Kumar Dusa , Richard Allen Bailey , Archana Venugopal , John Anthony Rodriguez , Michael Allen Ball

IPC: G11C17/18 , G11C17/16

CPC classification number: G11C17/18 , G11C17/165

Abstract: A fuse-programmable register or memory location having a plurality of fusible links of differing electrical characteristics in parallel. In one embodiment, three fusible links with different resistances are provided, such that application of a programming voltage non-uniformly distributes the current among the links, allowing varying voltages to selectively blow one or more of the links. Sensing of the programmed state is performed by applying a voltage across the parallel links and measuring the current in comparison with a plurality of reference currents. Reduction in the overhead chip area per bit and in the serial data communication latency are obtained.

77.

发明授权
Integration of backside heat spreader for thermal management 有权

公开(公告)号：US09698075B2

公开(公告)日：2017-07-04

申请号：US15210970

申请日：2016-07-15

Applicant: Texas Instruments Incorporated

Inventor： Archana Venugopal , Marie Denison , Luigi Colombo , Hiep Nguyen , Darvin Edwards

IPC: H01L23/373 , H01L23/00 , H01L21/48 , H01L23/367

CPC classification number: H01L23/373 , H01L21/4871 , H01L21/4889 , H01L23/367 , H01L23/3675 , H01L24/03 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/94 , H01L2224/03416 , H01L2224/0345 , H01L2224/03452 , H01L2224/0361 , H01L2224/0401 , H01L2224/04026 , H01L2224/05073 , H01L2224/05078 , H01L2224/05082 , H01L2224/05166 , H01L2224/05187 , H01L2224/05193 , H01L2224/05558 , H01L2224/05578 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/05687 , H01L2224/05693 , H01L2224/08165 , H01L2224/131 , H01L2224/16225 , H01L2224/291 , H01L2224/2919 , H01L2224/29191 , H01L2224/2929 , H01L2224/29339 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/73204 , H01L2224/73265 , H01L2224/83447 , H01L2224/94 , H01L2924/00014 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2924/00 , H01L2924/0665 , H01L2924/04941 , H01L2924/014 , H01L2924/01006 , H01L2924/0503 , H01L2924/01005 , H01L2924/01074 , H01L2224/45099 , H01L2224/03

Abstract: A microelectronic device includes semiconductor device with a component at a front surface of the semiconductor device and a backside heat spreader layer on a back surface of the semiconductor device. The backside heat spreader layer is 100 nanometers to 3 microns thick, has an in-plane thermal conductivity of at least 150 watts/meter-° K, and an electrical resistivity less than 100 micro-ohm-centimeters.

78.

发明申请
Fusible Link Cell with Dual Bit Storage 有权
Title translation: 具有双位存储的可熔链路单元

公开(公告)号：US20170018311A1

公开(公告)日：2017-01-19

申请号：US15146049

申请日：2016-05-04

Applicant: Texas Instruments Incorporated

Inventor： Sunil Kumar Dusa , Richard Allen Bailey , Archana Venugopal , John Anthony Rodriguez , Michael Allen Ball

IPC: G11C17/18 , G11C17/16

CPC classification number: G11C17/18 , G11C17/165

Abstract: A fuse-programmable register or memory location having a plurality of fusible links of differing electrical characteristics in parallel. In one embodiment, three fusible links with different resistances are provided, such that application of a programming voltage non-uniformly distributes the current among the links, allowing varying voltages to selectively blow one or more of the links. Sensing of the programmed state is performed by applying a voltage across the parallel links and measuring the current in comparison with a plurality of reference currents. Reduction in the overhead chip area per bit and in the serial data communication latency are obtained.

Abstract translation: 熔丝可编程寄存器或存储器位置具有并联的具有不同电特性的多个可熔链路。在一个实施例中，提供具有不同电阻的三个可熔链路，使得编程电压的施加不均匀地分布在链路之间的电流，允许变化的电压选择性地吹送一个或多个链路。通过跨多个并联链路施加电压并且与多个参考电流相比测量电流来执行编程状态的感测。获得每位开销芯片面积的减少和串行数据通信延迟。