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93 条记录 (耗时 0.034 秒)

    Method for preparing a narrow angle defined trench in a substrate
    72.
    发明授权
    Method for preparing a narrow angle defined trench in a substrate 失效
    在衬底中制备窄角限定沟槽的方法

    公开(公告)号：US5672537A

    公开(公告)日：1997-09-30

    申请号：US714276

    申请日：1996-09-17

    申请人： Daniel A. Carl ,  Donald M. Kenney ,  Walter E. Mlynko ,  Son Van Nguyen

    发明人： Daniel A. Carl ,  Donald M. Kenney ,  Walter E. Mlynko ,  Son Van Nguyen

    IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/763 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/76

    CPC分类号： H01L27/10861 ,  H01L21/763 ,  Y10S148/05

    摘要： Polysilicon (20) in a trench (21) is etched at an angle to produce a conductor within the trench that has shape characteristics which approximate the shadow of the side wall (26) of the trench (21) closest the beam source. Specifically, when the first side wall (26) is closest the beam source and the second side wall (27) is furthest from the beam source, the polysilicon on the first side wall (26) is almost as high as the first side wall (26), while the polysilicon on the more exposed side wall (27) is considerably lower than the first side wall (26) and approximates the shadow of the first side wall (26) on the second side wall (27) relative to the beam. The polysilicon (20) in the trench (21) may be in the shape of a solid angled block approximating the shadow line from the top of side wall (26) to side wall (27); however, it is preferred that the polysilicon take the form of a conformal layer in trench (21) prior to etching such that the polysilicon ultimately has an angled "U" shape which approximates the shadow line. Contact is made to the polysilicon (20) using strap (23) that electrically connects the side wall (26) with the polysilicon (20). Strap (23) is sized such that it does not extend to the opposite side wall (27) of trench (21), thereby avoiding short circuits. Having the polysilicon (20) approximate the shadow line of the etch permits narrowing the distance between adjacent straps (23) and (24) in an array without the risk of creating a short circuit.

    摘要翻译： 在沟槽（21）中的多晶硅（20）以一定角度蚀刻，以在沟槽内产生具有接近距离光束源的沟槽（21）的侧壁（26）的阴影的形状特征的导体。 具体地说，当第一侧壁（26）最靠近光束源和第二侧壁（27）离光束源最远时，第一侧壁（26）上的多晶硅几乎与第一侧壁（ 而更暴露的侧壁（27）上的多晶硅比第一侧壁（26）低得多，并且相对于光束近似于第二侧壁（27）上的第一侧壁（26）的阴影 。 沟槽（21）中的多晶硅（20）可以是从侧壁（26）的顶部到侧壁（27）近似阴影线的实心角块的形状; 然而，优选的是，多晶硅在蚀刻之前在沟槽（21）中具有保形层的形式，使得多晶硅最终具有接近阴影线的成角度的“U”形。 使用将侧壁（26）与多晶硅（20）电连接的带（23）与多晶硅（20）接触。 带（23）的尺寸使得其不延伸到沟槽（21）的相对侧壁（27），从而避免短路。 使多晶硅（20）近似于蚀刻线的阴影线允许在阵列中使相邻带（23）和（24）之间的距离变窄，而不会产生短路。

    Low temperature plasma oxidation process
    73.
    发明授权
    Low temperature plasma oxidation process 失效
    低温等离子体氧化工艺

    公开(公告)号：US5330935A

    公开(公告)日：1994-07-19

    申请号：US915752

    申请日：1992-07-21

    申请人： David M. Dobuzinsky ,  David L. Harmon ,  Srinandan R Kasi ,  Donald M. Kenney ,  Son Van Nguyen ,  Tue Nguyen ,  Pai-Hung Pan

    发明人： David M. Dobuzinsky ,  David L. Harmon ,  Srinandan R Kasi ,  Donald M. Kenney ,  Son Van Nguyen ,  Tue Nguyen ,  Pai-Hung Pan

    IPC分类号： C23C8/36 ,  H01L21/31 ,  H01L21/316 ,  H01L21/321 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/02

    CPC分类号： H01L21/32105 ,  H01L21/02238 ,  H01L21/02252 ,  H01L21/31662 ,  Y10S148/118 ,  Y10S257/90

    摘要： A process for forming a thin film on a surface of a semiconductor device. The process involves formation of a silicon dioxide film by plasma enhanced thermal oxidation, employing a mixture of ozone and oxygen which are generated separately from the reactor chamber in a volume ratio of about 1-10/1, preferably about 5-7/1, at a temperature generally below 440.degree. C., preferably about 350.degree.-400.degree. C. The process is used to form sidewall oxide spacers on polysilicon gates for field effect transistors. A relatively fast oxidation rate is achieved at a temperature significantly below that employed in conventional oxidation processes, and this serves to reduce dopant diffusion from the polysilicon. In addition, the resulting film demonstrates low stress with good conformal step coverage of the polysilicon gates. Another use of the process is to grow thin gate oxides and oxide-nitride-oxide with a thickness of less than 100.ANG.. An oxide film of uniform thickness is formed by controlling the temperature, RF power, exposure time and oxygen/ozone ratio for thin gate oxide (

    摘要翻译： 一种在半导体器件的表面上形成薄膜的工艺。 该方法包括通过等离子体增强的热氧化形成二氧化硅膜，采用臭氧和氧的混合物，其以反应器室分开产生，体积比约为1-10 / 1，优选约5-7 / 1， 在一般低于440℃，优选约350-400℃的温度下进行。该方法用于在场效应晶体管的多晶硅栅上形成侧壁氧化物间隔物。 在显着低于常规氧化工艺中使用的温度下实现相对较快的氧化速率，这用于减少掺杂剂从多晶硅的扩散。 此外，所得膜表现出低应力，并具有多晶硅栅极的良好的共形台阶覆盖。 该方法的另一个用途是生长厚度小于100安培的薄栅氧化物和氧化物 - 氮化物 - 氧化物。 通过控制ULSI FET制造中薄栅氧化物（<100 ANGSTROM）应用的温度，RF功率，曝光时间和氧/臭氧比，形成均匀厚度的氧化膜。

    Enclosed nanotube structure and method for forming
    76.
    发明授权
    Enclosed nanotube structure and method for forming 失效
    封闭纳米管结构和形成方法

    公开(公告)号：US07781267B2

    公开(公告)日：2010-08-24

    申请号：US11419329

    申请日：2006-05-19

    申请人： Jeffrey Peter Gambino ,  Son Van Nguyen

    发明人： Jeffrey Peter Gambino ,  Son Van Nguyen

    IPC分类号： H01L21/82

    CPC分类号： B82Y10/00 ,  G11C13/025 ,  H01L21/7682 ,  H01L29/0665 ,  H01L29/685 ,  H01L29/86 ,  H01L51/0048 ,  H01L51/0554 ,  H01L2221/1094

    摘要： A semiconductor device and associated method for forming. The semiconductor device comprises an electrically conductive nanotube formed over a first electrically conductive member such that a first gap exists between a bottom side the electrically conductive nanotube and a top side of the first electrically conductive member. A second insulating layer is formed over the electrically conductive nanotube. A second gap exists between a top side of the electrically conductive nanotube and a first portion of the second insulating layer. A first via opening and a second via opening each extend through the second insulating layer and into the second gap.

    摘要翻译： 一种半导体器件及相关的成型方法。 半导体器件包括形成在第一导电构件上的导电纳米管，使得第一间隙存在于导电纳米管的底侧和第一导电构件的顶侧之间。 在导电性纳米管上形成第二绝缘层。 在导电纳米管的顶侧和第二绝缘层的第一部分之间存在第二间隙。 第一通孔开口和第二通孔开口各自延伸穿过第二绝缘层并进入第二间隙。

    Advanced multilayer dielectric cap with improved mechanical and electrical properties
    77.
    发明授权
    Advanced multilayer dielectric cap with improved mechanical and electrical properties 失效
    先进的多层介质盖，具有改善的机械和电气性能

    公开(公告)号：US07737052B2

    公开(公告)日：2010-06-15

    申请号：US12042873

    申请日：2008-03-05

    申请人： Ritwik Bhatia ,  Griselda Bonilla ,  Alfred Grill ,  Joshua L. Herman ,  Son Van Nguyen ,  E. Todd Ryan ,  Hosadurga Shobha

    发明人： Ritwik Bhatia ,  Griselda Bonilla ,  Alfred Grill ,  Joshua L. Herman ,  Son Van Nguyen ,  E. Todd Ryan ,  Hosadurga Shobha

    IPC分类号： H01L21/31 ,  H01L21/469 ,  H01L23/58 ,  H01L23/48

    CPC分类号： H01L21/76834 ,  H01L21/02348 ,  H01L21/76832

    摘要： A dielectric cap, interconnect structure containing the same and related methods are disclosed. The inventive dielectric cap includes a multilayered dielectric material stack wherein at least one layer of the stack has good oxidation resistance, Cu diffusion and/or substantially higher mechanical stability during a post-deposition curing treatment, and including Si—N bonds at the interface of a conductive material such as, for example, Cu. The dielectric cap exhibits a high compressive stress and high modulus and is still remain compressive stress under post-deposition curing treatments for, for example: copper low k back-end-of-line (BEOL) nanoelectronic devices, leading to less film and device cracking and improved reliability.

    摘要翻译： 公开了包含相同方法和相关方法的电介质盖，互连结构。 本发明的电介质盖包括多层介电材料堆叠，其中叠层的至少一层在后沉积固化处理期间具有良好的抗氧化性，Cu扩散和/或显着更高的机械稳定性，并且包括Si-N键在 导电材料，例如Cu。 电介质盖表现出高压缩应力和高模量，并且在后沉积固化处理时仍然保持压应力，例如：铜低k后端（BEOL）纳米电子器件，导致较少的膜和器件 开裂和可靠性提高。

    Ultra low k plasma enhanced chemical vapor deposition processes using a single bifunctional precursor containing both a SiCOH matrix functionality and organic porogen functionality
    78.
    发明授权
    Ultra low k plasma enhanced chemical vapor deposition processes using a single bifunctional precursor containing both a SiCOH matrix functionality and organic porogen functionality 失效
    使用含有SiCOH基质官能团和有机致孔剂功能的单一双功能前体的超低k等离子体增强化学气相沉积方法

    公开(公告)号：US07491658B2

    公开(公告)日：2009-02-17

    申请号：US10964254

    申请日：2004-10-13

    申请人： Son Van Nguyen ,  Stephen McConnell Gates ,  Deborah A. Neumayer ,  Alfred Grill

    发明人： Son Van Nguyen ,  Stephen McConnell Gates ,  Deborah A. Neumayer ,  Alfred Grill

    IPC分类号： H01L21/31

    CPC分类号： C23C16/401 ,  H01L21/02126 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/02362 ,  H01L21/3122 ,  H01L21/31633 ,  H01L21/31695 ,  Y10T428/249921

    摘要： A method for fabricating a SiCOH dielectric material comprising Si, C, O and H atoms from a single organosilicon precursor with a built-in organic porogen is provided. The single organosilicon precursor with a built-in organic porogen is selected from silane (SiH4) derivatives having the molecular formula SiRR1R2R3, disiloxane derivatives having the molecular formula R4R5R6—Si—O—Si—R7R8R9, and trisiloxane derivatives having the molecular formula R10R11R12—Si—O—Si—R13R14—O—Si—R15R16R17 where R and R1-17 may or may not be identical and are selected from H, alkyl, alkoxy, epoxy, phenyl, vinyl, allyl, alkenyl or alkynyl groups that may be linear, branched, cyclic, polycyclic and may be functionalized with oxygen, nitrogen or fluorine containing substituents. In addition to the method, the present application also provides SiCOH dielectrics made from the inventive method as well as electronic structures that contain the same.

    摘要翻译： 提供了由具有内置有机致孔剂的单一有机硅前体制备包含Si，C，O和H原子的SiCOH电介质材料的方法。 具有内置有机致孔剂的单一有机硅前体选自具有分子式SiRR1R2R3的硅烷（SiH4）衍生物，具有分子式为R4R5R6-Si-O-Si-R7R8R9的二硅氧烷衍生物和分子式为R10R11R12- Si-O-Si-R13R14-O-Si-R15R16R17其中R和R1-17可以相同也可以不相同，并且可以选自H，烷基，烷氧基，环氧基，苯基，乙烯基，烯丙基，烯基或炔基， 直链，支链，环状，多环，并且可以被含氧，含氮或氟的取代基官能化。 除了该方法之外，本申请还提供了由本发明方法制备的SiCOH电介质以及含有该SiCOH的电子结构。

    Fuse Element Using Low-K Dielectric
    79.
    发明申请
    Fuse Element Using Low-K Dielectric 审中-公开
    使用低K电介质的保险丝元件

    公开(公告)号：US20080157268A1

    公开(公告)日：2008-07-03

    申请号：US11618749

    申请日：2006-12-30

    申请人： Deok-kee Kim ,  Anil K. Chinthakindi ,  Kelly Malone ,  Son Van Nguyen ,  Byeongju Park

    发明人： Deok-kee Kim ,  Anil K. Chinthakindi ,  Kelly Malone ,  Son Van Nguyen ,  Byeongju Park

    IPC分类号： H01L23/525

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A programmable structure such as a write once read many (WORM) or one time programmable read only memories (OTPROM) is disclosed herein. The structure includes a first conductor (such as copper) positioned within a substrate and a metal cap on the first conductor. A low-k dielectric is on the substrate and the metal cap. A tantalum nitride resistor is on the dielectric, and the resistor is positioned above the metal cap such that a programmable region of the dielectric is positioned between the resistor and the metal cap. The first conductor (including the metal cap), the programmable region of the dielectric, and the resistor form a metal-insulator-metal capacitor. Further, the programmable region of the dielectric is adapted to be permanently changed from heat produced by the resistor when a voltage difference is applied to the first and second ends of the resistor, respectively, through the first and second contacts. Thus, the capacitor comprises a first capacitance before the programmable region is permanently changed by the heat from the resistor and comprises a second capacitance after the programmable region is permanently changed by the heat from the resistor.

    摘要翻译： 这里公开了诸如一次写入一次读取（WORM）或一次可编程只读存储器（OTPROM）的可编程结构。 该结构包括位于基板内的第一导体（例如铜）和第一导体上的金属盖。 低k电介质位于基板和金属盖上。 电介质上有一个氮化钽电阻器，电阻器位于金属帽的上方，使电介质的可编程区域位于电阻器和金属帽之间。 第一导体（包括金属盖），电介质的可编程区域和电阻器形成金属 - 绝缘体 - 金属电容器。 此外，电介质的可编程区域分别适用于当通过第一和第二触点将电压差分别施加到电阻器的第一和第二端时由电阻器产生的热量永久地改变。 因此，电容器包括在可编程区域被来自电阻器的热量永久地变化之前的第一电容，并且在可编程区域被来自电阻器的热量永久地改变之后包括第二电容。