公开(公告)号：US20160233224A1

公开(公告)日：2016-08-11

申请号：US14614811

申请日：2015-02-05

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Hyoung Seub Rhie

IPC: H01L27/115

CPC classification number: H01L27/1157 ,  H01L27/11565 ,  H01L27/11582

Abstract: A three-dimensional integrated circuit nonvolatile memory array includes a memory array of vertical channel NAND flash strings connected between an upper layer connection bit line and a substrate which includes one or more elevated source regions disposed on at least one side of each row of NAND flash strings so that each NAND flash string includes a lower select transistor with a first channel portion that runs perpendicular to the surface of the substrate through a vertical channel string body, a second channel portion that runs parallel to the surface of the substrate, and a third channel portion that runs perpendicular to the surface of the substrate through the elevated source region.

Abstract translation: 三维集成电路非易失性存储器阵列包括连接在上层连接位线和衬底之间的垂直通道NAND闪存串的存储器阵列，其包括设置在每行NAND闪存的至少一侧上的一个或多个升高的​​源极区域 使得每个NAND闪存串包括具有第一通道部分的下选择晶体管，第一通道部分通过垂直通道串体垂直于衬底的表面延伸，第二通道部分平行于衬底的表面延伸， 通道部分，其通过升高的源区域垂直于衬底的表面延伸。

公开(公告)号：US09384838B2

公开(公告)日：2016-07-05

申请号：US14590541

申请日：2015-01-06

Applicant: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.

Inventor： Hyoung Seub Rhie

IPC: G11C16/10 ,  G11C16/08 ,  G11C8/08 ,  G11C11/408 ,  G11C16/04

CPC classification number: G11C16/08 ,  G11C8/08 ,  G11C11/4085 ,  G11C16/0483

Abstract: A non-volatile memory device having a memory array organized into a plurality of memory blocks, having either planar memory cells or stacks of cells. Row decoding circuitry of the memory device is configured to select a group of the plurality of memory blocks in response to a first row address, and to select a memory block of the group for receiving row signals in response to a second row address. Row decoding circuitry associated with each group of memory blocks can have a row pitch spacing that is greater than a row pitch spacing of a single memory block and less than or equal to a total row pitch spacing corresponding to the group of memory blocks.

公开(公告)号：US09343152B2

公开(公告)日：2016-05-17

申请号：US14460963

申请日：2014-08-15

Applicant: Conversant IP Management Inc.

Inventor： Hyoung Seub Rhie

IPC: G11C16/04 ,  H01L27/115

CPC classification number: G11C16/0483 ,  G11C16/0416 ,  H01L27/1157 ,  H01L27/11578

Abstract: A three-dimensional integrated circuit non-volatile memory array includes a memory array with first and second NAND memory cell string stacks having opposite orientations, where each NAND memory cell string includes a plurality of transistors and a source line contact connected in series between a bit line and string extension region which extends from the source line contact and past a first self-aligned SSL gate electrode located on a peripheral end of the NAND memory cell string, and also includes a string select transistor formed with a second self-aligned SSL connected in series between the bit line and the plurality of transistors, where the first and second self-aligned SSL gate electrodes are shared between adjacent NAND memory cell strings having opposite orientations.

Abstract translation: 三维集成电路非易失性存储器阵列包括具有相反取向的第一和第二NAND存储器单元串组的存储器阵列，其中每个NAND存储器单元串包括多个晶体管，以及串联连接在一位 线和串延伸区域，其从源极线接触延伸并且经过位于NAND存储器单元串的外围端上的第一自对准SSL栅电极，并且还包括形成有第二自对准SSL连接的串选择晶体管 串联在位线和多个晶体管之间，其中第一和第二自对准SSL栅电极在具有相反取向的相邻NAND存储器单元串之间共享。

公开(公告)号：US20160071825A1

公开(公告)日：2016-03-10

申请号：US14826251

申请日：2015-08-14

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Byoung Jin CHOI

IPC: H01L25/065 ,  G11C11/401

CPC classification number: H01L25/0657 ,  G11C5/06 ,  G11C7/10 ,  G11C7/1066 ,  G11C7/1093 ,  G11C11/401 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4097 ,  G11C29/023 ,  G11C29/028 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method and apparatus for organizing memory for a computer system including a plurality of memory devices, connected to a logic device, particularly a memory system having a plurality of stacked memory dice connected to a logic die, with the logic device having capability to analyze and compensate for differing delays to the stacked devices stacking multiple dice divided into partitions serviced by multiple buses connected to a logic die, to increase throughput between the devices and logic device allowing large scale integration of memory with self-healing capability.

公开(公告)号：US20160064410A1

公开(公告)日：2016-03-03

申请号：US14938259

申请日：2015-11-11

Applicant: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.

Inventor： Hyoung Seub RHIE

IPC: H01L27/115 ,  G11C16/14

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  G11C16/14 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

Abstract: A flash device comprising a well and a U-shaped flash cell string, the U-shaped flash cell string built directly on a substrate adjacent the well. The U-shaped flash cell string comprises one portion parallel to a surface of the substrate, comprising a junctionless bottom pass transistor, and two portions perpendicular to the surface of the substrate that comprise a string select transistor at a first top of the cell string, a ground select transistor at a second top of the cell string, a string select transistor drain, and a ground select transistor source.

Abstract translation: 包括阱和U形闪存单元串的闪存器件，U形闪存单元串直接构建在与阱相邻的衬底上。 U形闪存单元串包括平行于衬底的表面的一个部分，包括无连接底部传输晶体管，以及垂直于衬底表面的两个部分，其包括在电池串的第一顶部的串选择晶体管， 在单元串的第二顶部的接地选择晶体管，串选择晶体管漏极和接地选择晶体管源。

公开(公告)号：US09240227B2

公开(公告)日：2016-01-19

申请号：US11594564

申请日：2006-11-08

Applicant: Hong Beom Pyeon ,  Jin-Ki Kim ,  HakJune Oh

Inventor： Hong Beom Pyeon ,  Jin-Ki Kim ,  HakJune Oh

IPC: G06F13/28 ,  G11C7/10 ,  G06F13/42 ,  G11C5/06 ,  G06F12/06 ,  G11C16/06

CPC classification number: G11C7/10 ,  G06F12/0623 ,  G06F13/4247 ,  G06F13/4256 ,  G11C5/066 ,  G11C16/06

Abstract: A technique for serially coupling devices in a daisy chain cascading arrangement. Devices are coupled in a daisy chain cascade arrangement such that outputs of a first device are coupled to inputs of a second device later in the daisy chain to accommodate the transfer of information, such as data, address and command information, and control signals to the second device from the first device. The devices coupled in the daisy chain comprise a serial input (SI) and a serial output (SO). Information is input to a device via the SI. The information is output from the device via the SO. The SO of an earlier device in the daisy chain cascade is coupled to the SI of a device later in the daisy chain cascade. Information input to the earlier device via the device's SI is passed through the device and output from the device via the device's SO. The information is then transferred to the later device's SI via the connection from the earlier device's SO and the later device's SI.

Abstract translation: 用于串联菊花链级联装置的技术。 设备以菊花链级联布置耦合，使得第一设备的输出耦合到菊花链之后的第二设备的输入，以适应诸如数据，地址和命令信息等信息以及控制信号到 第二设备从第一设备。 耦合在菊花链中的器件包括串行输入（SI）和串行输出（SO）。 信息通过SI输入到设备。 信息通过SO从设备输出。 菊花链级联中的早期器件的SO与菊花链级联的器件的SI耦合。 通过设备的SI输入到较早的设备的信息通过设备并通过设备的SO从设备输出。 然后，信息通过早期设备的SO和后期设备的SI的连接传输到后期设备的SI。

公开(公告)号：US09202931B2

公开(公告)日：2015-12-01

申请号：US13829392

申请日：2013-03-14

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Hyoung Seub Rhie

IPC: H01L29/792 ,  H01L27/115

CPC classification number: H01L27/1157 ,  H01L21/28282 ,  H01L21/30604 ,  H01L27/11524 ,  H01L27/11551 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

Abstract: Described herein is a structure and method of manufacturing for a memory device with a thin silicon body. The memory device may be a semiconductor comprising: a first dielectric of a first width; a second dielectric of a second width, the second width less than the first width; and a thin film polycrystalline silicon (poly-Si) on sidewalls of the second dielectric.

Abstract translation: 这里描述了一种制造具有薄硅体的存储器件的结构和方法。 存储器件可以是半导体，其包括：第一宽度的第一电介质; 第二宽度的第二电介质，所述第二宽度小于所述第一宽度; 以及在第二电介质的侧壁上的薄膜多晶硅（poly-Si）。

公开(公告)号：US09158344B2

公开(公告)日：2015-10-13

申请号：US13689070

申请日：2012-11-29

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Hong Beom Pyeon

IPC: G06F1/20 ,  G06F1/18 ,  H01L25/18 ,  G06F15/78 ,  G11C11/401

CPC classification number: G06F1/18 ,  G06F1/203 ,  G06F15/78 ,  G11C11/401 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A multi-chip package has a substrate with electrical contacts for connection to an external device. A CPU die is disposed on the substrate and is in communication with the substrate. The CPU die has a plurality of processor cores occupying a first area of the CPU die, and an SRAM cache occupying a second area of the CPU die. A DRAM cache is disposed on the CPU die and is in communication with the CPU die. The DRAM cache has a plurality of stacked DRAM die. The plurality of stacked DRAM dies are substantially aligned with the second area of the CPU die, and substantially do not overlap the first area of the CPU die. A multi-chip package having a DRAM cache disposed on the substrate and a CPU die disposed on the DRAM cache is also disclosed.

Abstract translation: 多芯片封装具有具有用于连接到外部设备的电触点的基板。 CPU芯片设置在基板上并且与基板连通。 CPU管芯具有占用CPU管芯的第一区域的多个处理器核和占据CPU管芯的第二区域的SRAM缓存。 DRAM缓存器设置在CPU管芯上并与CPU管芯通信。 DRAM高速缓存具有多个堆叠的DRAM裸片。 多个堆叠的DRAM裸片基本上与CPU裸片的第二区域对准，并且基本上不与CPU裸片的第一区域重叠。 还公开了具有设置在基板上的DRAM高速缓存和设置在DRAM高速缓存上的CPU管芯的多芯片封装。

公开(公告)号：US09117527B2

公开(公告)日：2015-08-25

申请号：US14158116

申请日：2014-01-17

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： Jin-Ki Kim

IPC: G11C16/04 ,  G11C16/08 ,  G11C8/08 ,  G11C8/10 ,  G11C16/10

CPC classification number: G11C16/08 ,  G11C8/08 ,  G11C8/10 ,  G11C15/046 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26

Abstract: A flash memory device having at least one bank, where the each bank has an independently configurable page size. Each bank includes at least two memory planes having corresponding page buffers, where any number and combination of the memory planes are selectively accessed at the same time in response to configuration data and address data. The configuration data can be loaded into the memory device upon power up for a static page configuration of the bank, or the configuration data can be received with each command to allow for dynamic page configuration of the bank. By selectively adjusting a page size the memory bank, the block size is correspondingly adjusted.

Abstract translation: 具有至少一个存储体的闪速存储器件，其中每个存储体具有可独立配置的页面大小。 每个存储体包括至少两个具有对应页面缓冲器的存储器平面，其中响应于配置数据和地址数据，同时选择性地访问存储器层的任何数量和组合。 在上电时，可以将组态数据加载到存储设备中，以进行存储体的静态页面配置，或者可以通过每个命令接收配置数据以允许存储体的动态页面配置。 通过选择性地调整存储体的页面大小，相应地调整块大小。

公开(公告)号：US20150161072A1

公开(公告)日：2015-06-11

申请号：US14625858

申请日：2015-02-19

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Peter B. Gillingham

IPC: G06F13/42 ,  G11C7/10

CPC classification number: G06F13/4234 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/3253 ,  G06F1/3275 ,  G06F1/3287 ,  G06F13/1689 ,  G11C7/1072 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2924/00014 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151 ,  Y02D10/17 ,  Y02D10/171 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

Abstract: A semiconductor memory device including a plurality of memory die and a controller die. The controller die is connected to an internal control bus. The controller die is configured to provide to a selected one of the memory die an internal read command responsive to an external read command. The selected memory die is configured to provide read data to the controller in response to the internal read command; wherein latency between receipt by the controller die of the external read command and receipt of the read data from the selected memory die differs for at least two of the memory die when selected as the selected memory die.

Abstract translation: 一种包括多个存储器管芯和一个控制器管芯的半导体存储器件。 控制器管芯连接到内部控制总线。 控制器管芯被配置为响应于外部读取命令向存储器管芯中的所选择的一个提供内部读取命令。 所选择的存储器管芯被配置为响应于内部读取命令向控制器提供读取数据; 其中当被选择为所选择的存储器管芯时，由所述控制器管芯接收所述外部读取命令和从所选择的存储器管芯接收到所读取的数据的等待时间对于所述存储器管芯中的至少两个而言是不同的