公开(公告)号：US09543450B2

公开(公告)日：2017-01-10

申请号：US14440787

申请日：2012-12-04

申请人： Institute of Microelectronics, Chinese Academy of Sciences

发明人： Huilong Zhu

IPC分类号： H01L29/788 ,  H01L29/66 ,  H01L29/10 ,  H01L29/49 ,  H01L21/28 ,  H01L29/423 ,  H01L29/51 ,  H01L21/265

CPC分类号： H01L29/7881 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/28273 ,  H01L29/1095 ,  H01L29/42324 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66825

摘要： Semiconductor devices and methods for manufacturing the same are provided. In one embodiment, the method may include: forming a first shielding layer on a substrate, and forming one of source and drain regions with the first shielding layer as a mask; forming a second shielding layer on the substrate, and forming the other of the source and drain regions with the second shielding layer as a mask; removing a portion of the second shielding layer which is next to the other of the source and drain regions; forming a first gate dielectric layer and floating gate layer; forming a mask layer as a spacer on a sidewall of a remaining portion of the second shielding layer, and patterning the floating gate layer with the mask layer as a mask, and then removing the mask layer; and forming a second gate dielectric layer, and forming a gate conductor as a spacer on the sidewall of the remaining portion of the second shielding layer.

摘要翻译： 提供半导体器件及其制造方法。 在一个实施例中，该方法可以包括：在衬底上形成第一屏蔽层，并且将第一屏蔽层作为掩模形成源区和漏区之一; 在所述基板上形成第二屏蔽层，并且以所述第二屏蔽层为掩模形成所述源极和漏极区域中的另一个; 去除所述源极和漏极区域中另一个旁边的所述第二屏蔽层的一部分; 形成第一栅介质层和浮栅; 在所述第二屏蔽层的剩余部分的侧壁上形成作为间隔物的掩模层，并将所述掩模层的浮栅层图案化为掩模，然后除去掩模层; 以及形成第二栅极电介质层，并且在所述第二屏蔽层的剩余部分的侧壁上形成作为间隔物的栅极导体。

公开(公告)号：US09515169B2

公开(公告)日：2016-12-06

申请号：US14904140

申请日：2013-10-22

申请人： Institute of Microelectronics, Chinese Academy of Sciences

发明人： Haizhou Yin ,  Yunfei Liu

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/311 ,  H01L21/762 ,  H01L29/06

CPC分类号： H01L29/66795 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/31116 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7851

摘要： There is provided a FinFET fabricating method, comprising: a. providing a substrate ; b. forming a fin on the substrate; c. forming a channel protective layer on the fin; d. forming a shallow trench isolation on both sides of the fin; e. forming a sacrificial gate stack and a spacer on the top surface and sidewalls of the channel region which is in the middle of the fin; f. forming source/drain regions in both ends of the fin; g. depositing an interlayer dielectric layer on the sacrificial gate stack and the source/drain regions, planarizing later to expose the sacrificial gate stack; h. removing the sacrificial gate stack stack to form a sacrificial gate vacancy and expose the channel region and the channel protective layer; i. covering a portion of the semiconductor structure in one end of the fin with a photoresist layer; j. removing a portion of the spacer not covered; k. removing the photoresist layer and filling a gate stack in the sacrificial gate vacancy; l. planarizing the semiconductor structure formed by the foregoing steps to expose the channel protective layer and forming a first separated gate stack and a second separated gate stack. Comparing with the prior art, control ability of independent-gate-voltage FinFET can be effectively improved and it is good for device performance.

摘要翻译： 提供了一种FinFET制造方法，包括：a。 提供衬底; b。 在基板上形成翅片; C。 在翅片上形成通道保护层; d。 在鳍的两侧形成浅沟槽隔离; e。 在鳍的中间的沟道区的顶表面和侧壁上形成牺牲栅叠层和间隔物; F。 在鳍的两端形成源/漏区; G。 在所述牺牲栅极堆叠和所述源极/漏极区域上沉积层间电介质层，以稍后平坦化以暴露所述牺牲栅极堆叠; H。 去除牺牲栅极堆叠堆叠以形成牺牲栅极空位并暴露沟道区域和沟道保护层; 一世。 用光致抗蚀剂层覆盖鳍的一端中的半导体结构的一部分; j。 去除未覆盖的间隔件的一部分; k。 去除光致抗蚀剂层并在牺牲栅极空位中填充栅极堆叠; l。 平面化由上述步骤形成的半导体结构以暴露沟道保护层并形成第一分离的栅极堆叠和第二分离栅极堆叠。 与现有技术相比，可以有效提高独立栅极电压FinFET的控制能力，对器件性能有好处。

公开(公告)号：US09502560B2

公开(公告)日：2016-11-22

申请号：US14797762

申请日：2015-07-13

申请人： Institute of Microelectronics, Chinese Academy of Sciences

发明人： Huilong Zhu

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L21/265 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/308 ,  H01L21/02 ,  H01L29/165

CPC分类号： H01L29/7848 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/26513 ,  H01L21/3083 ,  H01L21/31053 ,  H01L21/31111 ,  H01L29/0638 ,  H01L29/0673 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/6681 ,  H01L29/7851

摘要： Provided are a semiconductor device and a method of manufacturing the same. An example device may include: a substrate having a well formed therein, the well including a first section and a second section, wherein the first section has a lower doping concentration and is closer to a surface of the substrate than the second section; a fin structure formed on the surface of the substrate; an isolation layer formed on the surface of the substrate, wherein the isolation layer exposes a portion of the fin structure, which serves as a fin for the semiconductor device; a gate stack formed on the isolation layer and intersecting the fin, wherein a Punch-Through Stopper (PTS) is formed in only a region directly under a portion of the fin where the fin intersects the gate stack.

摘要翻译： 提供半导体器件及其制造方法。 示例性装置可以包括：其中具有良好形成的衬底，所述阱包括第一部分和第二部分，其中所述第一部分具有较低的掺杂浓度并且比所述第二部分更靠近所述衬底的表面; 形成在所述基板的表面上的翅片结构; 形成在所述基板的表面上的隔离层，其中所述隔离层暴露所述鳍结构的作为所述半导体器件的翅片的部分; 形成在隔离层上并与翅片相交的栅极叠层，其中穿孔止动器（PTS）仅形成在翅片的直接与栅极叠层相交的部分下方的区域中。

公开(公告)号：US09442230B2

公开(公告)日：2016-09-13

申请号：US14144222

申请日：2013-12-30

申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

发明人： Hailiang Li ,  Changqing Xie ,  Ming Liu ,  Dongmei Li ,  Lina Shi ,  Xiaoli Zhu

IPC分类号： G06K7/10 ,  G02B5/18 ,  G03F7/075 ,  G03F7/20 ,  G03F7/40

CPC分类号： G02B5/1871 ,  G02B5/1809 ,  G02B5/1838 ,  G02B5/1857 ,  G02B2005/1804 ,  G03F7/0757 ,  G03F7/2059 ,  G03F7/40

摘要： A method of manufacturing a sub-wavelength extreme ultraviolet metal transmission grating is disclosed. In one aspect, the method comprises forming a silicon nitride self-supporting film window on a back surface of a silicon-based substrate having both surfaces polished, then spin-coating a silicon nitride film on a front surface of the substrate with an electron beam resist HSQ. Then, performing electron beam direct writing exposure on the HSQ, developing and fixing to form a plurality of grating line patterns and a ring pattern surrounding the grating line patterns. Then depositing a chrome material on the front surface of the substrate through magnetron sputtering. Then, removing the chrome material inside the ring pattern. Then, growing a gold material on the front surface of the substrate through atomic layer deposition. Lastly, removing the gold material on the chrome material outside the ring pattern as well as on and between the grating line patterns, thereby only retaining the gold material on sidewalls of the grating line patterns.

摘要翻译： 公开了一种制造亚波长极紫外金属透射光栅的方法。 在一个方面，该方法包括在硅衬底的背表面上形成氮化硅自支撑膜窗，其两面被抛光，然后用电子束在衬底的前表面上旋涂氮化硅膜 抵制HSQ。 然后，在HSQ上执行电子束直接写入曝光，显影和固定以形成围绕光栅线图案的多个光栅线图案和环形图案。 然后通过磁控溅射在基板的前表面上沉积铬材料。 然后，移除环形图案内的铬材料。 然后，通过原子层沉积在基板的前表面上生长金材料。 最后，除去环形图案之外的铬材料上的金材料以及光栅线图案之间和之间的金材料，从而仅将金材料保留在光栅线图案的侧壁上。

公开(公告)号：US09419112B2

公开(公告)日：2016-08-16

申请号：US14647360

申请日：2012-12-17

申请人： Institute of Microelectronics, Chinese Academy of Sciences

发明人： Huilong Zhu ,  Jun Luo ,  Chunlong Li

IPC分类号： H01L21/265 ,  H01L21/306 ,  H01L29/66 ,  H01L29/78 ,  H01L21/3105 ,  H01L21/321 ,  H01L29/10 ,  H01L29/16 ,  H01L29/165

CPC分类号： H01L29/6681 ,  H01L21/265 ,  H01L21/30604 ,  H01L21/3086 ,  H01L21/31053 ,  H01L21/32115 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7848 ,  H01L29/7851

摘要： A method for manufacturing a fin structure is provided. A method according to an embodiment may include: forming a patterned pattern transfer layer on a substrate; forming a first spacer on sidewalls of the pattern transfer layer; forming a second spacer on sidewalls of the first spacer; selectively removing the pattern transfer layer and the first spacer; and patterning the substrate with the second spacer as a mask, so as to form an initial fin.

摘要翻译： 提供一种制造翅片结构的方法。 根据实施例的方法可以包括：在衬底上形成图案化图案转移层; 在所述图案转移层的侧壁上形成第一间隔物; 在所述第一间隔件的侧壁上形成第二间隔件; 选择性地去除图案转印层和第一间隔物; 并用第二间隔物作为掩模图案化衬底，以形成初始鳍。

公开(公告)号：US09418843B2

公开(公告)日：2016-08-16

申请号：US14760890

申请日：2013-01-17

申请人： Institute of Microelectronics, Chinese Academy of Sciences

发明人： Dongmei Li ,  Xin Chen ,  Shengfa Liang ,  Jiebin Niu ,  Peiwen Zhang ,  Yu Liu ,  Xiaojing Li ,  Shuang Zhan ,  Hao Zhang ,  Qing Luo ,  Changqing Xie ,  Ming Liu

IPC分类号： H01L21/00 ,  H01L21/02 ,  H01L21/465 ,  G01N33/00 ,  B82Y10/00 ,  B82Y40/00

CPC分类号： H01L21/02565 ,  B82Y10/00 ,  B82Y40/00 ,  G01N33/004 ,  G01N33/005 ,  H01L21/02422 ,  H01L21/02581 ,  H01L21/02603 ,  H01L21/02614 ,  H01L21/465 ,  Y02A50/243

摘要： The present disclosure provides a method for manufacturing ordered nanowires array of NiO doped with Pt in situ, comprising: growing a Ni layer on a high-temperature resistant and insulated substrate; applying a photoresist on the Ni layer, pattering a pattern region of the ordered nanowires array by applying electron beam etching on the photoresist, growing Ni on the pattern region of the ordered nanowires array, peeling off the photoresist by acetone and etching the surface of the Ni layer by ion beam etching so as to etch off the Ni layer grown on the surface of the substrate and to leave the Ni on the pattern region of the ordered nanowires array to form the ordered Ni nanowires array; dipping the ordered Ni nanowires array into a solution of H2PtCl6 so as to displace Pt on the Ni nanowires array by a displacement reaction; and oxidizing the Ni nanowires array attached with Pt in an oxidation oven to obtain the ordered nanowires array of NiO doped with Pt. The present invention is simple and practical and the sensitivity and reliability of the doped sensor on the gas of CO and H2 are greatly improved.

摘要翻译： 本公开提供了一种用于制造原位掺杂有Pt的NiO的有序纳米线阵列的方法，包括：在耐高温和绝缘的衬底上生长Ni层; 在Ni层上施加光致抗蚀剂，通过在光致抗蚀剂上施加电子束蚀刻来图案化有序纳米线阵列的图案区域，在有序纳米线阵列的图案区域上生长Ni，用丙酮剥离光致抗蚀剂并蚀刻 Ni层，以便蚀刻生长在衬底表面上的Ni层，并将Ni留在有序纳米线阵列的图案区上以形成有序的Ni纳米线阵列; 将有序的Ni纳米线阵列浸入H2PtCl6溶液中，通过置换反应置换Ni纳米线阵列上的Pt; 并在氧化炉中氧化附着有Pt的Ni纳米线阵列，以获得掺杂有Pt的NiO的有序纳米线阵列。 本发明简单实用，掺杂传感器对CO和H2气体的灵敏度和可靠性大大提高。

公开(公告)号：US09418835B2

公开(公告)日：2016-08-16

申请号：US14662963

申请日：2015-03-19

申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

发明人： Guilei Wang ,  Jinbiao Liu ,  Junfeng Li

IPC分类号： H01L21/02 ,  H01L21/265

CPC分类号： H01L21/0217 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02312 ,  H01L21/02329 ,  H01L21/0234 ,  H01L21/265

摘要： The present disclosure provides a method of manufacturing a semiconductor device having silicon nitride with a tensile stress, the method comprising: c1) introducing and pre-stabilizing NH3 gas and N2 gas; c2) introducing silane; c3) igniting the gases by a radio-frequency source; c4) depositing SiN; and c5) processing the SiN by using a nitrogen ion implantation. According to the present disclosure, the nitrogen content in the SiN film can be enhanced by the nitrogen ion implantation and impinging, thereby increasing the density of the film. In this way, the acid resistance of the SiN with tensile stress is enhanced, so that the SiN with tensile stress may be integrated in a dual-strained liner of a gate-last process, so as to effectively improve the properties and reliability of the device.

摘要翻译： 本公开提供一种制造具有拉伸应力的氮化硅的半导体器件的方法，所述方法包括：c1）引入和预稳定NH 3气体和N 2气体; c2）引入硅烷; c3）用射频源点燃气体; c4）沉积SiN; 和c5）通过使用氮离子注入来处理SiN。 根据本公开，通过氮离子注入和冲击，可以提高SiN膜中的氮含量，从而提高膜的密度。 以这种方式，具有拉伸应力的SiN的耐酸性得到提高，使得具有拉伸应力的SiN可以集成在最后工艺的双应变衬里中，从而有效地提高了最终工艺的性能和可靠性 设备。

公开(公告)号：US09401425B2

公开(公告)日：2016-07-26

申请号：US14437755

申请日：2012-11-27

申请人： Institute of Microelectronics, Chinese Academy of Sciences

发明人： Huilong Zhu ,  Haizhou Yin ,  Zhijiong Luo

IPC分类号： H01L29/78 ,  H01L29/10 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/06 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/762 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165

CPC分类号： H01L29/7848 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/3086 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823481 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636

摘要： A semiconductor structure is disclosed. The semiconductor structure comprises: a substrate (130), a support structure (131), a base region (100), a gate stack, a spacer (240), and a source/drain region, wherein the gate stack is located on the base region (100), and the base region (100) is supported on the substrate (130) by the support structure (131), wherein the sidewall cross-section of the support structure (131) is in a shape of a concave curve; an isolation structure (123) is formed beneath the edges on both sides of the base region (100), wherein a portion of the isolation structure (123) is connected to the substrate (130); a cavity (112) is formed between the isolation structure (123) and the support structure (131); and there exists a source/drain region at least on both sides of the base region (100) and the isolation structure (123). Accordingly, a method for manufacturing the semiconductor structure is also disclosed.

摘要翻译： 公开了半导体结构。 半导体结构包括：衬底（130），支撑结构（131），基极区（100），栅极堆叠，间隔物（240）和源极/漏极区，其中栅极堆叠位于 基部区域（100），并且所述基部区域（100）由所述支撑结构（131）支撑在所述基板（130）上，其中所述支撑结构（131）的侧壁横截面为凹曲线 ; 隔离结构（123）形成在基部区域（100）的两侧的边缘之下，其中隔离结构（123）的一部分连接到基板（130）; 在隔离结构（123）和支撑结构（131）之间形成空腔（112）; 并且至少在基极区域（100）和隔离结构（123）的两侧存在源极/漏极区域。 因此，还公开了一种用于制造半导体结构的方法。

公开(公告)号：US09397104B2

公开(公告)日：2016-07-19

申请号：US13509891

申请日：2011-11-23

申请人： Huilong Zhu ,  Qingqing Liang

发明人： Huilong Zhu ,  Qingqing Liang

IPC分类号： H01L21/70 ,  H01L27/11 ,  H01L21/84 ,  H01L27/12

CPC分类号： H01L27/1104 ,  H01L21/845 ,  H01L27/1211

摘要： In one embodiment, a SRAM cell may include a substrate and a first Fin Field Effect Transistor (FinFET) and a second FinFET formed on the substrate. The first FinFET may include a first fin which is formed in a semiconductor layer provided on the substrate and abuts the semiconductor layer, and the second FinFET may include a second fin which is formed in the semiconductor layer and abuts the semiconductor layer. The semiconductor layer may include a plurality of semiconductor sub-layers. The first and second fins can include different number of the semiconductor sub-layers and have different heights from each other.

摘要翻译： 在一个实施例中，SRAM单元可以包括衬底和形成在衬底上的第一Fin场效应晶体管（FinFET）和第二FinFET。 第一FinFET可以包括形成在衬底上的半导体层中，并与该半导体层相邻的第一鳍片，并且第二鳍片FET可以包括形成在半导体层中并邻接半导体层的第二鳍片。 半导体层可以包括多个半导体子层。 第一和第二散热片可以包括不同数量的半导体子层，并且彼此具有不同的高度。

公开(公告)号：US20160204199A1

公开(公告)日：2016-07-14

申请号：US14904871

申请日：2013-10-22

申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

发明人： Haizhou Yin

IPC分类号： H01L29/10 ,  H01L29/161 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L29/08 ,  H01L29/165

CPC分类号： H01L29/1033 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66492 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A MOSFET structure and a method for manufacturing the same are disclosed. The method comprises: a. providing a substrate (100); b. forming a silicon germanium channel layer (101), a dummy gate structure (200) and a sacrificial spacer (102); c. removing the silicon germanium channel layer and portions of the substrate which are not covered by the dummy gate structure (200) and located under both sides of the dummy gate structure 200, so as to form vacancies (201); d. selectively epitaxially growing a first semiconductor layer (300) on the semiconductor structure to fill bottom and sidewalls of the vacancies (201); and e. removing the sacrificial spacer (102) and filling a second semiconductor layer (400) in the vacancies which are not filled by the first semiconductor layer (300). In the semiconductor structure of the present disclosure, carrier mobility in the channel can be increased, negative effects induced by the short channel effects can be suppressed, and device performance can be enhanced.

摘要翻译： 公开了一种MOSFET结构及其制造方法。 该方法包括：a。 提供衬底（100）; b。 形成硅锗沟道层（101），伪栅极结构（200）和牺牲间隔物（102）; C。 去除未被所述虚拟栅极结构（200）覆盖并位于所述虚拟栅极结构200的两侧的所述硅锗沟道层和所述衬底的部分，以形成空位（201）; d。 在所述半导体结构上选择性地外延生长第一半导体层（300）以填充所述空位（201）的底部和侧壁; 和e。 去除所述牺牲间隔物（102）并在未被所述第一半导体层（300）填充的空位中填充第二半导体层（400）。 在本公开的半导体结构中，可以增加通道中的载流子迁移率，可以抑制由短通道效应引起的负面影响，并且可以提高器件性能。