公开(公告)号：US09541809B2

公开(公告)日：2017-01-10

申请号：US14470969

申请日：2014-08-28

Applicant: Samsung Display Co., Ltd.

Inventor： Yun-Seok Han ,  Seul-Ki Kim ,  Seung-Jin Kim ,  Jeong-Hyun Lee

IPC: G02F1/136 ,  G02F1/1362 ,  H01L27/12 ,  G02F1/1345

CPC classification number: G02F1/136259 ,  G02F1/13458 ,  G02F1/136286 ,  H01L27/124

Abstract: An array substrate includes a plurality of data lines, a plurality of gamma lines, a repair pad, a repair line, an inspection pad and an inspection line. The data lines transmit a data voltage to an active region. The gamma lines apply a gamma reference voltage to generate the data voltage. The repair pad repairs the data line. The repair line extends from the repair pad. The repair line is disposed adjacent to the gamma line. The inspection pad applies an inspection signal. The inspection line extends from the inspection pad. The inspection line is connected to the data lines. The gamma lines are connected to the inspection line.

Abstract translation: 阵列基板包括多条数据线，多条伽马线，修理焊盘，修理线，检查焊盘和检查线。 数据线将数据电压传送到有源区。 伽马线应用伽马参考电压以产生数据电压。 修理垫修理数据线。 修理线从修理垫延伸。 修复线设置在伽马线附近。 检查垫应用检查信号。 检查线从检查板延伸。 检查线连接到数据线。 伽马线连接到检查线。

公开(公告)号：US20160357069A1

公开(公告)日：2016-12-08

申请号：US15139623

申请日：2016-04-27

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Heung Shik PARK ,  Jae Hoon JUNG ,  Dan Bi YANG ,  Min-Joo HAN ,  Ji Phyo HONG ,  Ki Chul SHIN

IPC: G02F1/1337 ,  G02F1/1343 ,  G02F1/1341 ,  G02F1/1362 ,  G02F1/1333 ,  G02F1/1345 ,  G02F1/1368

CPC classification number: G02F1/133753 ,  G02F1/133788 ,  G02F1/13458 ,  G02F1/13624 ,  G02F1/136286 ,  G02F2001/133761 ,  G02F2001/134345

Abstract: A liquid crystal display includes a first substrate, pixel electrodes disposed on the first substrate and including a first sub-pixel electrode and a second sub-pixel electrode separated from each other and positioned in one pixel area, gate lines connected to the pixel electrodes, data lines connected to the pixel electrodes, reference voltage lines connected to the second sub-pixel electrode of the pixel electrodes, a second substrate facing the first substrate, a common electrode disposed on the second substrate, and a liquid crystal layer positioned between the first substrate and the second substrate and including liquid crystal molecules, a first initial pretilt angle of the liquid crystal molecules corresponding to the first sub-pixel electrode for the second substrate surface is larger than a second initial pretilt angle of the liquid crystal molecules corresponding to the second sub-pixel electrode for the second substrate surface.

Abstract translation: 液晶显示器包括第一基板，设置在第一基板上的像素电极，包括彼此分离并位于一个像素区域中的第一子像素电极和第二子像素电极，连接到像素电极的栅极线， 连接到像素电极的数据线，连接到像素电极的第二子像素电极的参考电压线，面对第一衬底的第二衬底，设置在第二衬底上的公共电极以及位于第一衬底之间的液晶层 基板和第二基板并且包括液晶分子，对应于第二基板表面的第一子像素电极的液晶分子的第一初始预倾角大于对应于第二基板表面的液晶分子的第二初始预倾角 用于第二衬底表面的第二子像素电极。

公开(公告)号：US20160349581A1

公开(公告)日：2016-12-01

申请号：US15234113

申请日：2016-08-11

Applicant: Japan Display Inc.

Inventor： Tomonori NISHINO ,  Syou YANAGISAWA ,  Kentaro AGATA ,  Hiroyuki ABE ,  Takayuki SUZUKI

IPC: G02F1/1362 ,  G02F1/1345

CPC classification number: G02F1/136204 ,  G02F1/133351 ,  G02F1/13458

Abstract: This invention envisages flexible wiring substrate terminals serving to connect with the wires for preventing dielectric breakdown caused by static electricity during the manufacturing process, and reducing the number of the flexible wiring substrate terminals. On a mother TFT substrate, signal lines extend over each liquid crystal cell in a manner flanking a scribe line between the adjacent liquid crystal cells. The signal lines of each liquid crystal cell are connected with connecting lines striding the scribe line. This reduces the number of static electricity countermeasure wires extending from the flexible wiring substrate terminals of each liquid crystal cell. Once completed, the individual liquid crystal cells are separated from one another, with no adverse effects caused by the connecting lines.

Abstract translation: 本发明设想用于连接导线的柔性布线基板端子，用于防止在制造过程中由静电导致的电介质击穿，并且减少柔性布线基板端子的数量。 在母TFT基板上，信号线以相邻液晶单元之间的划线侧面的方式延伸到每个液晶单元上。 每个液晶单元的信号线与跨越划线的连接线连接。 这就减少了从每个液晶单元的柔性布线基板端子延伸的静电对抗线的数量。 一旦完成，各个液晶单元彼此分离，没有由连接线引起的不利影响。

公开(公告)号：US20160343741A1

公开(公告)日：2016-11-24

申请号：US14769196

申请日：2015-02-27

Applicant: BOE TECHNOLOGY GROUP CO., LTD. ,  HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD

Inventor： Liping LIU ,  Chunlei DONG

IPC: H01L27/12 ,  G02F1/1345 ,  G02F1/1341 ,  G09G3/36 ,  G02F1/1362

CPC classification number: H01L27/1244 ,  G02F1/133512 ,  G02F1/1339 ,  G02F1/1341 ,  G02F1/13452 ,  G02F1/13458 ,  G02F1/136209 ,  G02F1/136286 ,  G02F2001/136222 ,  G09G3/3655

Abstract: A display device is disclosed and includes an array substrate and a color filter substrate. The color filter substrate includes a display region, a peripheral black matrix region and a process reserved blank region which are sequentially arranged from inside to outside. A bonding line is provided within the peripheral black matrix region and/or the process reserved blank region and electrically connected to a structure to be bonded on the array substrate through a connection structure.

Abstract translation: 公开了一种显示装置，包括阵列基板和滤色器基板。 滤色器基板包括从内到外依次布置的显示区域，外围黑矩阵区域和处理保留空白区域。 在外围黑色矩阵区域和/或处理保留空白区域内提供接合线，并且通过连接结构电连接到待结合到阵列基板上的结构。

公开(公告)号：US09496063B2

公开(公告)日：2016-11-15

申请号：US14268879

申请日：2014-05-02

Applicant: Samsung Display Co., Ltd.

Inventor： Young Joo Choi ,  Seung Ho Jung ,  Joon Geol Kim ,  Kang Moon Jo

IPC: H01L29/739 ,  H01B1/02 ,  G02F1/1333 ,  G02F1/1343 ,  G02F1/1345 ,  G02F1/1362

CPC classification number: H01B1/026 ,  G02F1/133345 ,  G02F1/134363 ,  G02F1/13439 ,  G02F1/13458 ,  G02F2001/134318 ,  G02F2001/13629 ,  G02F2001/136295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A liquid crystal display and a method of fabricating a liquid crystal display (LCD), the LCD including a substrate; gate wiring including a gate pad, a gate electrode, and a gate line, which are formed on the substrate; a gate insulating layer disposed on the gate wiring; an electrode pattern including a connecting electrode, which is disposed on the gate insulating layer and is electrically connected to the gate pad, a source electrode and a drain electrode, which partially overlap the gate electrode; a pixel electrode, which is electrically connected to the drain electrode; a data line, which intersects the gate line; a semiconductor layer disposed on the gate electrode; first auxiliary wiring overlapping the data line and spaced from the semiconductor layer; and second auxiliary wiring overlapping the gate line.

Abstract translation: 液晶显示器和制造液晶显示器（LCD）的方法，所述LCD包括基板; 栅极布线，包括形成在基板上的栅极焊盘，栅电极和栅极线; 设置在栅极布线上的栅极绝缘层; 电极图案，其包括设置在所述栅极绝缘层上并与所述栅极焊盘电连接的连接电极，所述栅电极部分地重叠的源电极和漏电极; 与漏电极电连接的像素电极; 与栅极线相交的数据线; 设置在所述栅电极上的半导体层; 第一辅助布线与数据线重叠并与半导体层间隔开; 并且第二辅助配线与栅极线重叠。

公开(公告)号：US09494818B2

公开(公告)日：2016-11-15

申请号：US14512677

申请日：2014-10-13

Applicant: Apple Inc.

Inventor： Kwang Soon Park ,  Byung Duk Yang ,  Christopher L. Boitnott ,  Chun-Yao Huang ,  Kuan-Ying Lin ,  Kyung-Wook Kim ,  Mohd Fadzli A. Hassan ,  Shih Chang Chang ,  Supriya Goyal ,  Yong Kwan Kim ,  Yu-Cheng Chen

IPC: G02F1/1333 ,  G02F1/1335 ,  G02F1/13 ,  G02F1/1345

CPC classification number: G02F1/133512 ,  G02F1/1309 ,  G02F1/13452 ,  G02F1/13458

Abstract: A display may have a liquid crystal layer sandwiched between a thin-film transistor layer and a color filter layer. An upper polarizer may be placed on top of the thin-film transistor layer. A lower polarizer may be placed under the color filter layer. Components may be bonded to bond pads on the inner surface of the thin-film transistor layer using anisotropic conductive film. Bond quality may be assessed by probing probe pads that are coupled to the bond pads or by visually inspecting the bond pads through the thin-film transistor layer. Opaque masking material in the inactive area may be provided with openings to accommodate the bond pads. Additional opaque masking material may be placed on the underside of the upper polarizer and on the upper surface of the thin-film transistor layer to block the openings from view following visual inspection.

Abstract translation: 显示器可以具有夹在薄膜晶体管层和滤色器层之间的液晶层。 上偏振器可以放置在薄膜晶体管层的顶部。 下偏振器可以放置在滤色器层下方。 可以使用各向异性导电膜将部件结合到薄膜晶体管层的内表面上的接合焊盘。 可以通过探测耦合到接合焊盘的探针焊盘或通过目视检查通过薄膜晶体管层的焊盘来评估焊盘质量。 在不活动区域中的不透明掩模材料可以设置有开口以容纳接合焊盘。 附加的不透明掩模材料可以放置在上偏振器的下侧和薄膜晶体管层的上表面上，以在视觉检查之后阻挡开口。

公开(公告)号：US20160320682A1

公开(公告)日：2016-11-03

申请号：US15204597

申请日：2016-07-07

Applicant: Japan Display Inc.

Inventor： Kenji Kitajima ,  Ryouhei Suzuki

IPC: G02F1/1362 ,  G02F1/1345 ,  G02F1/1335 ,  G02F1/1339

CPC classification number: G02F1/136209 ,  G02F1/133512 ,  G02F1/133514 ,  G02F1/133528 ,  G02F1/1339 ,  G02F1/13439 ,  G02F1/1345 ,  G02F1/13458 ,  G02F1/136286 ,  G02F2201/121

Abstract: A liquid crystal display device includes a thin film transistor substrate having a pixel region and a frame region, and a color filter substrate. The frame region includes a first metal wire that surrounds the outside of the pixel region, and a second metal wire that is formed so as to surround the outside of the first metal wire. The first metal wire has at least one slit at an area overlapping with a seal material.

公开(公告)号：US20160320671A1

公开(公告)日：2016-11-03

申请号：US14782197

申请日：2015-01-20

Applicant: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD

Inventor： Qibiao LV ,  Xiaohui YAO

IPC: G02F1/1343 ,  H01L27/12 ,  G02F1/1368 ,  G02F1/1345 ,  G02F1/1362

CPC classification number: G02F1/134309 ,  G02F1/133707 ,  G02F1/134363 ,  G02F1/13439 ,  G02F1/13458 ,  G02F1/1362 ,  G02F1/136227 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/133302 ,  G02F2201/121 ,  G02F2201/123 ,  G02F2201/40 ,  H01L27/1214

Abstract: The present invention discloses a pixel unit and an array substrate. The pixel unit comprises: a plurality of pixel electrodes, including oblique pixel electrodes extending obliquely and transverse pixel electrodes located on edges of the oblique pixel electrodes and extending transversely, the plurality of pixel electrodes forming a display region having an opening region; and, a conductive unit which is located within the opening region and partially overlapped with projections of the oblique pixel electrodes, one corner of the conductive unit close to the oblique pixel units being an unfilled corner or a round corner. Accordingly, the impact of an electric field around the opening region on the electric field of the oblique pixel electrodes is reduced, and the impact on the liquid crystal orientation of the opening region is reduced; the dark fringe of pixels is improved; the aperture ratio of pixels is increased; and the quality of display is improved.

Abstract translation: 本发明公开了像素单元和阵列基板。 像素单元包括：多个像素电极，包括倾斜像素电极和位于倾斜像素电极的边缘上的横向像素电极，并且横向延伸，所述多个像素电极形成具有开口区域的显示区域; 以及导电单元，其位于所述开口区域内并部分地与所述倾斜像素电极的突起重叠，所述导电单元的靠近所述倾斜像素单元的一角是未填充角或圆角。 因此，围绕开口区域的电场对倾斜像素电极的电场的影响减小，并且对开口区域的液晶取向的影响减小; 像素的黑色边缘得到改善; 像素的开口率增加; 显示质量得到提高。

公开(公告)号：US09484287B2

公开(公告)日：2016-11-01

申请号：US14953390

申请日：2015-11-29

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinya Suzuki

IPC: H01L23/485 ,  H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L23/00 ,  G02F1/1345 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/311 ,  H01L27/13 ,  H01L29/78

CPC classification number: H01L24/14 ,  G02F1/13306 ,  G02F1/133345 ,  G02F1/134309 ,  G02F1/13439 ,  G02F1/1345 ,  G02F1/13458 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/133302 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/768 ,  H01L21/76819 ,  H01L23/485 ,  H01L23/522 ,  H01L23/528 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L27/13 ,  H01L29/7833 ,  H01L2224/02122 ,  H01L2224/0345 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05075 ,  H01L2224/051 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05553 ,  H01L2224/056 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/13005 ,  H01L2224/13006 ,  H01L2224/13009 ,  H01L2224/13013 ,  H01L2224/13022 ,  H01L2224/13027 ,  H01L2224/13144 ,  H01L2224/14153 ,  H01L2224/16225 ,  H01L2224/271 ,  H01L2224/2929 ,  H01L2224/29355 ,  H01L2224/29444 ,  H01L2224/32225 ,  H01L2224/81 ,  H01L2224/81191 ,  H01L2224/8185 ,  H01L2224/83101 ,  H01L2224/83203 ,  H01L2224/83851 ,  H01L2224/9211 ,  H01L2224/93 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1426 ,  H01L2924/15788 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2224/83 ,  H01L2924/00

Abstract: A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surface protection film formed to cover the top wiring layer is flattened by CMP.

公开(公告)号：US09484286B2

公开(公告)日：2016-11-01

申请号：US14953382

申请日：2015-11-29

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinya Suzuki

IPC: H01L23/485 ,  H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L23/00 ,  G02F1/1345 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/311 ,  H01L27/13 ,  H01L29/78

CPC classification number: H01L24/14 ,  G02F1/13306 ,  G02F1/133345 ,  G02F1/134309 ,  G02F1/13439 ,  G02F1/1345 ,  G02F1/13458 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/133302 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/768 ,  H01L21/76819 ,  H01L23/485 ,  H01L23/522 ,  H01L23/528 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L27/13 ,  H01L29/7833 ,  H01L2224/02122 ,  H01L2224/0345 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05075 ,  H01L2224/051 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05553 ,  H01L2224/056 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/13005 ,  H01L2224/13006 ,  H01L2224/13009 ,  H01L2224/13013 ,  H01L2224/13022 ,  H01L2224/13027 ,  H01L2224/13144 ,  H01L2224/14153 ,  H01L2224/16225 ,  H01L2224/271 ,  H01L2224/2929 ,  H01L2224/29355 ,  H01L2224/29444 ,  H01L2224/32225 ,  H01L2224/81 ,  H01L2224/81191 ,  H01L2224/8185 ,  H01L2224/83101 ,  H01L2224/83203 ,  H01L2224/83851 ,  H01L2224/9211 ,  H01L2224/93 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1426 ,  H01L2924/15788 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2224/83 ,  H01L2924/00

Abstract: A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surface protection film formed to cover the top wiring layer is flattened by CMP.