公开(公告)号：US06888230B1

公开(公告)日：2005-05-03

申请号：US09429297

申请日：1999-10-28

申请人： Masahiko Ogino ,  Takumi Ueno ,  Shuji Eguchi ,  Akira Nagai ,  Toshiya Satoh ,  Toshiaki Ishii ,  Hiroyoshi Kokaku ,  Tadanori Segawa ,  Nobutake Tsuyuno ,  Asao Nishimura ,  Ichiro Anjoh

发明人： Masahiko Ogino ,  Takumi Ueno ,  Shuji Eguchi ,  Akira Nagai ,  Toshiya Satoh ,  Toshiaki Ishii ,  Hiroyoshi Kokaku ,  Tadanori Segawa ,  Nobutake Tsuyuno ,  Asao Nishimura ,  Ichiro Anjoh

IPC分类号： H01L23/12 ,  H01L21/301 ,  H01L21/46 ,  H01L21/48 ,  H01L21/50 ,  H01L21/60 ,  H01L23/28 ,  H01L23/31 ,  H01L23/50 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/3171 ,  H01L23/3114 ,  H01L23/3164 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05026 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/1147 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2924/00012

摘要： Semiconductor devices, semiconductor wafers, and semiconductor modules are provided, wherein: the semiconductor device has a small warp; damage at the chip edge and cracks occurring in a dropping test are scarcely generated; and the semiconductor device is superior in mounting reliability and mass producibility. The semiconductor includes a semiconductor chip 64; a porous stress relaxing layer 3 provided on the plane, whereon circuits and electrodes are formed, of the semiconductor chip; a circuit layer 2 provided on the stress relaxing layer and connected to the electrodes; and external terminals 10 provided on the circuit layer; wherein an organic protecting film 7 is formed on the plane, opposite to the stress relaxing layer, of the semiconductor chip, and respective side planes of the stress relaxing layer, the semiconductor chip 6, and the protecting film 7 are exposed outside on the same plane.

摘要翻译： 提供半导体器件，半导体晶片和半导体模块，其中：半导体器件具有小的翘曲; 几乎不产生芯片边缘的损伤和在滴下试验中发生的裂纹; 半导体装置的安装可靠性和大规模生产性优异。 该半导体包括半导体芯片64; 设置在半导体芯片的形成有电路和电极的平面上的多孔应力缓和层3; 设置在应力缓和层上并与电极连接的电路层2; 和设置在电路层上的外部端子10; 其中在半导体芯片的与应力缓和层相反的平面上形成有机保护膜7，并且应力缓和层，半导体芯片6和保护膜7的各个侧面在外部暴露在外部 飞机

公开(公告)号：US06621154B1

公开(公告)日：2003-09-16

申请号：US09671364

申请日：2000-09-28

申请人： Toshiya Satoh ,  Masahiko Ogino ,  Tadanori Segawa ,  Takao Miwa ,  Akira Nagai ,  Akihiro Yaguchi ,  Ichiro Anjo ,  Asao Nishimura

发明人： Toshiya Satoh ,  Masahiko Ogino ,  Tadanori Segawa ,  Takao Miwa ,  Akira Nagai ,  Akihiro Yaguchi ,  Ichiro Anjo ,  Asao Nishimura

IPC分类号： H01L2329

CPC分类号： H01L23/293 ,  C08L9/02 ,  C08L13/00 ,  C08L63/00 ,  H01L23/485 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/13022 ,  H01L2924/0002 ,  H01L2924/09701 ,  C08L2666/08 ,  H01L2224/05552

摘要： A miniature semiconductor apparatus is outstanding in reflow resistance, temperature cycle property, and PCT resistance corresponding to high density packing, high densification, and speeding up of processing. The semiconductor apparatus has at least one stress cushioning layer on a semiconductor element with an electrode pad formed, having a conductor on the stress cushioning layer, having a conductor for conducting the electrode pad and conductor via a through hole passing through the stress cushioning layer between the electrode pad and the conductor, having an external electrode on the conductor, and having a stress cushioning layer in an area other than the area where the external electrode exists and a conductor protection layer on the conductor, wherein the stress cushioning layer includes crosslinking acrylonitrile-butadiene rubber having an epoxy resin which is solid at 25° C. and a carboxyl group.

摘要翻译： 一种微型半导体装置在耐回流性，温度循环特性以及PCT电阻方面具有突出优点，其对应于高密度填料，高密度化和加工加速。 所述半导体装置具有在半导体元件上具有至少一个应力缓冲层，所述至少一个应力缓冲层具有形成有电极焊盘的电极焊盘，所述电极焊盘在所述应力缓冲层上具有导体，所述导体用于通过穿过所述应力缓冲层的通孔 所述电极焊盘和所述导体在导体上具有外部电极，并且在外部电极存在的区域以外的区域和在导体上具有导体保护层的应力缓冲层，其中应力缓冲层包括交联丙烯腈 丁二烯橡胶，其具有在25℃下为固体的环氧树脂和羧基。

公开(公告)号：US06348741B1

公开(公告)日：2002-02-19

申请号：US09675011

申请日：2000-09-29

申请人： Masahiko Ogino ,  Takao Miwa ,  Toshiya Satoh ,  Akira Nagai ,  Tadanori Segawa ,  Akihiro Yaguchi ,  Ichiro Anjo ,  Asao Nishimura ,  Takumi Ueno

发明人： Masahiko Ogino ,  Takao Miwa ,  Toshiya Satoh ,  Akira Nagai ,  Tadanori Segawa ,  Akihiro Yaguchi ,  Ichiro Anjo ,  Asao Nishimura ,  Takumi Ueno

IPC分类号： H01L2348

CPC分类号： H01L23/3171 ,  H01L23/293 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05572 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/0101 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01043 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/15787 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/05124 ,  H01L2224/05147

摘要： A manufacturing method makes it possible to produce a semiconductor apparatus which is outstanding in mounting reliability at a high manufacturing yield rate. A semiconductor apparatus, in which, on the surface of a semiconductor chip with a circuit and an electrode formed thereon, a stress cushioning layer is provided, except for a part where the electrode is, has a wiring layer connected to the electrode on the stress cushioning layer, an external protection film on the wiring layer and stress cushioning layer, a window where a part of the wiring layer is exposed at a predetermined location of the external protection film, and an external electrode which is electrically connected to the wiring layer via the window. The stress cushioning layer, wiring layer, conductor, external protection film, and external electrode are formed on the inside of the end of the semiconductor chip.

摘要翻译： 制造方法使得可以以高的制造成品率制造突出的安装可靠性的半导体装置。 一种半导体装置，其中在其上形成有电路和电极的半导体芯片的表面上设置有应力缓冲层，除了电极的部分具有连接到电极上的布线层的应力 缓冲层，布线层上的外部保护膜和应力缓冲层，布线层的一部分在外部保护膜的预定位置露出的窗口，以及外部电极，其与布线层电连接，经由 窗户。 应力缓冲层，布线层，导体，外部保护膜和外部电极形成在半导体芯片的端部的内侧。

公开(公告)号：US5677045A

公开(公告)日：1997-10-14

申请号：US430553

申请日：1995-04-28

申请人： Akira Nagai ,  Masatsugu Ogata ,  Shuji Eguchi ,  Masahiko Ogino ,  Toshiaki Ishii ,  Masanori Segawa ,  Hiroyoshi Kokaku ,  Ryo Moteki ,  Ichiro Anjoh

发明人： Akira Nagai ,  Masatsugu Ogata ,  Shuji Eguchi ,  Masahiko Ogino ,  Toshiaki Ishii ,  Masanori Segawa ,  Hiroyoshi Kokaku ,  Ryo Moteki ,  Ichiro Anjoh

IPC分类号： B32B27/12 ,  H01L23/14 ,  H05K1/03 ,  B32B7/00 ,  B32B3/02 ,  B32B5/12 ,  B32B5/16

CPC分类号： B32B27/12 ,  H01L23/145 ,  H05K1/0373 ,  H01L2224/48227 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/3025 ,  H05K2201/015 ,  H05K2201/0209 ,  H05K2201/0212 ,  H05K2201/029 ,  H05K2201/068 ,  Y10S428/901 ,  Y10T428/23986 ,  Y10T428/24132 ,  Y10T428/254 ,  Y10T442/20 ,  Y10T442/209 ,  Y10T442/2123 ,  Y10T442/3854 ,  Y10T442/3919

摘要： A laminate capable of mounting semiconductor elements thereon; comprising an insulating layer which is constituted by a resin portion of sea-island structure and a woven reinforcement. The resin portion of sea-island structure is, for example, such that a resin as islands are dispersed in a resin as a matrix. Thus, the insulating layer exhibits a coefficient of thermal expansion of 3.0.about.10 (ppm/K) in a planar direction thereof and a glass transition temperature of 150.about.300 (.degree.C.). Owing to these physical properties, thermal stresses which the laminate undergoes in packaging the semiconductor elements thereon can be reduced, so that the connections of the laminate with the semiconductor elements can be made highly reliable.

摘要翻译： 能够在其上安装半导体元件的层压体; 包括由海岛结构的树脂部分和织造加强件构成的绝缘层。 例如，海岛结构的树脂部分使得岛状树脂以树脂为基体分散。 因此，绝缘层在其平面方向上的热膨胀系数为3.0D（ppm / K），玻璃化转变温度为150℃（℃）。 由于这些物理性质，可以减少层压体在其上封装半导体元件时的热应力，使得层压体与半导体元件的连接可以高度可靠。

公开(公告)号：US08288079B2

公开(公告)日：2012-10-16

申请号：US11622542

申请日：2007-01-12

申请人： Masahiko Ogino ,  Makoto Kaji ,  Hanako Yori

发明人： Masahiko Ogino ,  Makoto Kaji ,  Hanako Yori

IPC分类号： G03F7/028 ,  B29C35/08

CPC分类号： C08F2/48 ,  B82Y10/00 ,  B82Y40/00 ,  C08F220/18 ,  C08F222/1006 ,  C09D4/00 ,  G03F7/0002

摘要： A photocurable resin composition containing a photopolymerization initiator and a (meth)acrylate monomer and/or oligomer, said (meth)acrylate monomer or oligomer having a cyclic structure, in which the atomic weight of carbon (Mcr) in said cyclic structure and the number of whole carbon atoms (MTOT) in said composition have the relation of Mcr/MTOT>0.1, or the total number (N) of carbon atoms in said cyclic structure, the total number of carbon atoms (Nc) in said composition and the total number of oxygen atoms (No) have the relation of N/(Nc−No)

摘要翻译： 含有光聚合引发剂和（甲基）丙烯酸酯单体和/或低聚物的所述（甲基）丙烯酸酯单体或低聚物的光固化性树脂组合物，其中所述环状结构中的碳原子量（Mcr）和数量 在所述组合物中的全碳原子数（MTOT）具有Mcr / MTOT> 0.1的关系，或所述环状结构中的碳原子总数（N），所述组合物中的总碳数（Nc）和总计 氧原子数（No）具有N /（Nc-No）<4的关系，组成物的动力粘度为10mPa·s以下。 该低粘度光固化性树脂组合物具有优异的耐干蚀刻性，适用于光学纳米打印。

公开(公告)号：US07815706B2

公开(公告)日：2010-10-19

申请号：US10521818

申请日：2003-08-04

申请人： Koji Yamada ,  Masahiko Ogino ,  Nobuyasu Ezawa ,  Hiroshi Inoue

发明人： Koji Yamada ,  Masahiko Ogino ,  Nobuyasu Ezawa ,  Hiroshi Inoue

IPC分类号： C22B11/00

CPC分类号： C22B9/16 ,  C22B11/02 ,  C22B11/021 ,  C22B11/026 ,  C22B15/0054 ,  Y02P10/214

摘要： A method for recovering platinum group elements comprises charging into a closed electric furnace and melting, together with flux components and a reducing agent, a platinum group element-containing substance to be processed and a copper source material containing copper oxide, sinking molten metal of primarily metallic copper below a molten slag layer of primarily oxides, and enriching the platinum group elements in the molten metal sunk below, and is characterized in that molten slag whose copper content has decreased to 3.0 wt % or less is discharged from the electric furnace and that the copper source material charged into the electric furnace is a granular copper source material of a grain diameter of not less than 0.1 mm and not greater than 10 mm.

摘要翻译： 回收铂族元素的方法包括：向封闭的电炉中加入熔融物，与助熔剂成分和还原剂一起熔化待加工的含铂族元素的物质和含有氧化铜的铜源材料，主要沉入熔融金属 金属铜在主要氧化物的熔融渣层以下，并且将熔融金属中的铂族元素富集在下面，并且其特征在于，铜含量已降至3.0重量％以下的熔渣从电炉中排出， 装入电炉的铜源材料是粒径不小于0.1mm且不大于10mm的粒状铜源材料。

公开(公告)号：US20090087506A1

公开(公告)日：2009-04-02

申请号：US12191326

申请日：2008-08-14

申请人： Mitsuru Hasegawa ,  Masahiko Ogino

发明人： Mitsuru Hasegawa ,  Masahiko Ogino

IPC分类号： B29C33/36

CPC分类号： B29C59/04 ,  B29C2059/023 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/0002 ,  Y10S977/887

摘要： There is provided a fine pattern transfer, belt-shaped mold, with which a fine structure having a high aspect ratio can be formed rapidly and stably using nanoimprinting, and a fine pattern transfer system (a nanoimprint system) that employs this mold. According to the present invention, a nanoimprint mold includes: a belt-shaped support member; a plurality of stampers, for each of which a fine convex-and-concave pattern, to be transferred, is formed on one surface; and an adhesive member, to which the belt-shaped support member and the stampers are to be securely adhered, wherein the adhesive member includes a porous member and adhesive layers, which are deposited on either face of the porous member, for impregnating one part of the porous member, and wherein, for the porous member, a porous area that is not impregnated with the adhesive layers, is provided and positioned so as to sandwich the porous member between portions impregnated with the adhesive layers.

摘要翻译： 提供了一种精细图案转印，带状模具，利用其可以使用纳米压印快速且稳定地形成具有高纵横比的精细结构，并且使用该模具的精细图案转印系统（纳米压印系统）。 根据本发明，纳米压印模具包括：带状支撑构件; 在一个表面上形成多个刻印机，每个都要在其上形成要转印的细凹凸图案; 以及粘合构件，其中带状支撑构件和压模应牢固地粘附到该粘合构件上，其中粘合构件包括多孔构件和粘合剂层，其沉积在多孔构件的任一面上，用于浸渍一部分 多孔构件，并且其中，对于多孔构件，设置并定位未浸渍有粘合剂层的多孔区域，以将多孔构件夹在浸渍有粘合剂层的部分之间。

公开(公告)号：US07217992B2

公开(公告)日：2007-05-15

申请号：US10861523

申请日：2004-06-07

申请人： Masahiko Ogino ,  Takumi Ueno ,  Shuji Eguchi ,  Akira Nagai ,  Toshiya Satoh ,  Toshiaki Ishii ,  Hiroyoshi Kokaku ,  Tadanori Segawa ,  Nobutake Tsuyuno ,  Asao Nishimura ,  Ichiro Anjoh

发明人： Masahiko Ogino ,  Takumi Ueno ,  Shuji Eguchi ,  Akira Nagai ,  Toshiya Satoh ,  Toshiaki Ishii ,  Hiroyoshi Kokaku ,  Tadanori Segawa ,  Nobutake Tsuyuno ,  Asao Nishimura ,  Ichiro Anjoh

IPC分类号： H01L23/02 ,  H01L23/28 ,  H01L21/00

CPC分类号： H01L23/3171 ,  H01L23/3114 ,  H01L23/3164 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05026 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/1147 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2924/00012

摘要： Semiconductor devices,-semiconductor wafers, and semiconductor modules are provided: wherein the semiconductor device has a small warp; damages at chip edge and cracks in a dropping test are scarcely generated; and the semiconductor device is superior in mounting reliability and mass producibility.The semiconductor device 17 comprising: a semiconductor chip 64; a porous stress relaxing layer 3 provided on the plane, whereon circuits and electrodes are formed, of the semiconductor chip; a circuit layer 2 provided on the stress relaxing layer and connected to the electrodes; and external terminals 10 provided on the circuit layer; wherein an organic protecting film 7 is formed on the plane, opposite to the stress relaxing layer, of the semiconductor chip, and respective side planes of the stress relaxing layer, the semiconductor chip 6, and the protecting film 7 are exposed outside on a same plane.

摘要翻译： 提供半导体器件，半导体晶片和半导体模块：其中半导体器件具有小的翘曲; 几乎不产生芯片边缘的损坏和跌落试验中的裂纹; 半导体装置的安装可靠性和大规模生产性优异。 半导体器件17包括：半导体芯片64; 设置在半导体芯片的形成有电路和电极的平面上的多孔应力缓和层3; 设置在应力缓和层上并与电极连接的电路层2; 和设置在电路层上的外部端子10; 其中在半导体芯片的与应力缓和层相反的平面上形成有机保护膜7，并且应力缓和层，半导体芯片6和保护膜7的各个侧面在外部暴露在外部 飞机

公开(公告)号：US20070065757A1

公开(公告)日：2007-03-22

申请号：US11523559

申请日：2006-09-20

申请人： Masahiko Ogino ,  Ken Sawabe ,  Makoto Kaji ,  Hanako Yori

发明人： Masahiko Ogino ,  Ken Sawabe ,  Makoto Kaji ,  Hanako Yori

IPC分类号： G03C5/00

CPC分类号： G03F7/027 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/0002 ,  G03F7/0048

摘要： Provided is a new photo-curable resin composition which can be used in a photo nanoimprinting technology available for a photo nanoimprinting technology by which a substrate is processed with high accuracy. The photo-curable resin composition contains a photo-curable resin material essentially containing a (meth)acrylate, a reactive diluent, and a photo initiator. Preferably, the (meth)acrylate has a structure containing a benzene ring structure in its skeleton.

摘要翻译： 提供了一种新的可光固化树脂组合物，其可用于可用于以高精度处理基底的光纳米压印技术的光纳米压印技术。 光固化树脂组合物含有基本上含有（甲基）丙烯酸酯，反应性稀释剂和光引发剂的光固化树脂材料。 优选地，（甲基）丙烯酸酯在其骨架中具有含有苯环结构的结构。

公开(公告)号：US07038325B2

公开(公告)日：2006-05-02

申请号：US10830051

申请日：2004-04-23

申请人： Masahiko Ogino ,  Shuji Eguchi ,  Akira Nagai ,  Takumi Ueno ,  Masanori Segawa ,  Hiroyoshi Kokaku ,  Toshiaki Ishii ,  Ichiro Anjoh ,  Asao Nishimura ,  Chuichi Miyazaki ,  Mamoru Mita ,  Norio Okabe

发明人： Masahiko Ogino ,  Shuji Eguchi ,  Akira Nagai ,  Takumi Ueno ,  Masanori Segawa ,  Hiroyoshi Kokaku ,  Toshiaki Ishii ,  Ichiro Anjoh ,  Asao Nishimura ,  Chuichi Miyazaki ,  Mamoru Mita ,  Norio Okabe

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/50 ,  H01L23/3107 ,  H01L23/49572 ,  H01L23/49816 ,  H01L24/32 ,  H01L2224/29111 ,  H01L2224/73215 ,  H01L2924/0001 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2224/29099 ,  H01L2924/00

摘要： In a semiconductor device having a three-layered buffer layer comprising core layer 1 having interconnected foams such as a three-dimensional reticular structure and adhesive layers 2 provided on both sides of the core layer as a stress buffer layer between semiconductor chip 5 and wiring 4 to lessen a thermal stress generated between the semiconductor device and the package substrate, where a thickness ratio of the core layer 1 to total buffer layer is at least 0.2, the production process can be simplified by using such a buffer layer, thereby improving the mass production capacity and enhancing the package reliability.

摘要翻译： 在具有三层缓冲层的半导体器件中，作为在半导体芯片5和布线4之间的应力缓冲层，芯层1具有三维网状结构的互连泡沫的芯层1和设置在芯层两侧的粘合层2 为了减小半导体器件与封装衬底之间产生的热应力，其中芯层1与总缓冲层的厚度比至少为0.2，可以通过使用这种缓冲层来简化制造工艺，从而提高质量 生产能力和提高包装可靠性。