公开(公告)号：US09891261B2

公开(公告)日：2018-02-13

申请号：US14320598

申请日：2014-06-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Fen Chen ,  Mukta G. Farooq ,  John A. Griesemer ,  Chandrasekaran Kothandaraman ,  John M. Safran ,  Timothy D. Sullivan ,  Ping-Chuan Wang ,  Lijuan Zhang

IPC: H01L21/66 ,  G01R31/08 ,  H01L23/48

CPC classification number: G01R31/08 ,  G01R31/2856 ,  G01R31/2858 ,  H01L22/14 ,  H01L22/34 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure, such as a wafer, chip, IC, design structure, etc., includes a through silicon via (TSV) and an electromigration (EM) monitor. The TSV extends completely through a semiconductor chip and the EM monitor includes a plurality of EM wires proximately arranged about the TSV perimeter. An EM testing method includes forcing electrical current through EM monitor wiring arranged in close proximity to the perimeter of the TSV, measuring an electrical resistance drop across the EM monitor wiring, determining if an electrical short exists between the EM monitor wiring and the TSV from the measured electrical resistance, and/or determining if an early electrical open or resistance increase exists within the EM monitoring wiring due to TSV induced proximity effect.

公开(公告)号：US09391014B2

公开(公告)日：2016-07-12

申请号：US14825303

申请日：2015-08-13

Applicant: International Business Machines Corporation

Inventor： Kai D. Feng ,  Wai-Kin Li ,  Ping-Chuan Wang ,  Zhijian Yang

IPC: H01L23/522 ,  H01L23/528 ,  H04L9/32 ,  H05K1/02

CPC classification number: H01L23/5222 ,  H01L21/0274 ,  H01L21/3212 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/7684 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H04L9/3278 ,  H04L2209/12 ,  H05K1/0289 ,  Y10T29/49117 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A method for fabricating an interconnect function array includes forming a first plurality of conductive lines on a substrate, forming an insulator layer over the first plurality of conductive lines and the substrate, removing portions of the insulator layer to define cavities in the insulator layer that expose portions of the substrate and the first plurality of conductive lines, wherein the removal of the portions of the insulator layer results in a substantially random arrangement of cavities exposing portions of the substrate and the first plurality of conductive lines, depositing a conductive material in the cavities, and forming a second plurality of conductive lines on portions of the conductive material in the cavities and the insulator layer.

Abstract translation: 一种用于制造互连功能阵列的方法包括在衬底上形成第一多条导线，在第一多条导线和衬底之上形成绝缘体层，去除绝缘体层的部分以限定暴露在绝缘体层中的空腔 衬底和第一多个导电线的部分，其中去除绝缘体层的部分导致暴露衬底和第一多个导电线的部分的空腔的基本上随机的排列，在腔中沉积导电材料 并且在所述空腔和所述绝缘体层中的所述导电材料的部分上形成第二多个导电线。

公开(公告)号：US20160190005A1

公开(公告)日：2016-06-30

申请号：US15060685

申请日：2016-03-04

Applicant: International Business Machines Corporation

Inventor： Kai D. Feng ,  Wai-Kin Li ,  Ping-Chuan Wang ,  Zhijian Yang

IPC: H01L21/768 ,  H01L21/027 ,  H01L21/321

CPC classification number: H01L23/5222 ,  H01L21/0274 ,  H01L21/3212 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/7684 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H04L9/3278 ,  H04L2209/12 ,  H05K1/0289 ,  Y10T29/49117 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A method for fabricating an interconnect function array includes forming a first plurality of conductive lines on a substrate, forming an insulator layer over the first plurality of conductive lines and the substrate, removing portions of the insulator layer to define cavities in the insulator layer that expose portions of the substrate and the first plurality of conductive lines, wherein the removal of the portions of the insulator layer results in a substantially random arrangement of cavities exposing portions of the substrate and the first plurality of conductive lines, depositing a conductive material in the cavities, and forming a second plurality of conductive lines on portions of the conductive material in the cavities and the insulator layer.

公开(公告)号：US09354252B2

公开(公告)日：2016-05-31

申请号：US14560138

申请日：2014-12-04

Applicant: International Business Machines Corporation

Inventor： Robert D. Edwards ,  Oleg Gluschenkov ,  Louis V. Medina ,  Tso-Hui Ting ,  Ping-Chuan Wang ,  Yongchun Xin

IPC: G01R1/067 ,  G01R31/28 ,  G01R1/073

CPC classification number: G01R31/2891 ,  G01R1/06794 ,  G01R1/07364

Abstract: A wafer probing system includes a probe card assembly having a plurality of individual probe structures configured make contact with a semiconductor wafer mounted on a motor driven wafer chuck, with each probe structure configured with a pressure sensing unit integrated therewith; and a controller configured to drive the probe card assembly with one or more piezoelectric driver units response to feedback from the pressure sensing units of the individual probe structures.

公开(公告)号：US20150255410A1

公开(公告)日：2015-09-10

申请号：US14198711

申请日：2014-03-06

Applicant: International Business Machines Corporation

Inventor： Ronald G. Filippi ,  Erdem Kaltalioglu ,  Andrew T. Kim ,  Ping-Chuan Wang ,  Lijuan Zhang

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/768

CPC classification number: H01L24/05 ,  H01L23/481 ,  H01L24/03 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/94 ,  H01L2224/03312 ,  H01L2224/0332 ,  H01L2224/03426 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/03462 ,  H01L2224/0361 ,  H01L2224/03616 ,  H01L2224/039 ,  H01L2224/0391 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05012 ,  H01L2224/05015 ,  H01L2224/05018 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05187 ,  H01L2224/05552 ,  H01L2224/05557 ,  H01L2224/05559 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05671 ,  H01L2224/08145 ,  H01L2224/11312 ,  H01L2224/1132 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/1317 ,  H01L2224/13171 ,  H01L2224/13181 ,  H01L2224/13184 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/94 ,  H01L2924/12042 ,  H01L2924/35121 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/83 ,  H01L2224/80 ,  H01L2924/00014 ,  H01L2924/05442 ,  H01L2924/05042 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/00012 ,  H01L2224/034

Abstract: The present invention relates generally to flip chip technology and more particularly, to a method and structure for fabricating a mechanically anchored controlled collapse chip connection (C4) pad on a semiconductor structure. In an embodiment, a method is disclosed that may include forming a bonding pad having one or more anchor regions that extend into a semiconductor structure and may inhibit the bonding pad from physically separating from the TSV during temperature fluctuations.

Abstract translation: 本发明一般涉及倒装芯片技术，更具体地说，涉及用于在半导体结构上制造机械锚定的控制崩溃芯片连接（C 4）焊盘的方法和结构。 在一个实施例中，公开了一种方法，其可以包括形成具有延伸到半导体结构中的一个或多个锚定区域的焊盘，并且可能在温度波动期间阻止焊盘与TSV物理分离。

公开(公告)号：US20150255387A1

公开(公告)日：2015-09-10

申请号：US14721460

申请日：2015-05-26

Applicant: International Business Machines Corporation

Inventor： Ronald G. Filippi ,  Erdem Kaltalioglu ,  Ping-Chuan Wang ,  Lijuan Zhang

IPC: H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76816 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a wiring structure for an integrated circuit device includes forming a first metal line within an interlevel dielectric (ILD) layer, and forming a second metal line in the ILD layer adjacent the first metal line; masking selected regions of the first and second metal lines; selectively plating metal cap regions over exposed regions of the first and second metal lines at periodic intervals such that a spacing between adjacent metal cap regions of an individual metal line corresponds to a critical length, L, at which a back stress gradient balances an electromigration force in the individual metal line, so as to suppress mass transport of electrons; and wherein the metal cap regions of the first metal line are formed at staggered locations with respect to the metal cap regions of the second metal line, along a common longitudinal axis.

公开(公告)号：US20150235944A1

公开(公告)日：2015-08-20

申请号：US14181897

申请日：2014-02-17

Applicant: International Business Machines Corporation

Inventor： Ronald G. Filippi ,  Erdem Kaltalioglu ,  Shahab Siddiqui ,  Ping-Chuan Wang ,  Lijuan Zhang

IPC: H01L23/525 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5252 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5223 ,  H01L23/53238 ,  H01L28/90 ,  H01L29/66181 ,  H01L29/945 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A through-silicon-via (TSV) structure is formed within a trench located within a semiconductor structure. The TSV structure may include a first electrically conductive liner layer located on an outer surface of the trench and a first electrically conductive structure located on the first electrically conductive liner layer, whereby the first electrically conductive structure partially fills the trench. A second electrically conductive liner layer is located on the first electrically conductive structure, a dielectric layer is located on the second electrically conductive liner layer, while a third electrically conductive liner layer is located on the dielectric layer. A second electrically conductive structure is located on the third electrically conductive liner layer, whereby the second electrically conductive structure fills a remaining opening of the trench.

Abstract translation: 在位于半导体结构内的沟槽内形成贯通硅通孔（TSV）结构。 TSV结构可以包括位于沟槽的外表面上的第一导电衬垫层和位于第一导电衬里层上的第一导电结构，由此第一导电结构部分地填充沟槽。 第二导电衬里层位于第一导电结构上，电介质层位于第二导电衬里层上，而第三导电衬垫层位于电介质层上。 第二导电结构位于第三导电衬里层上，由此第二导电结构填充沟槽的剩余开口。

公开(公告)号：US20150207505A1

公开(公告)日：2015-07-23

申请号：US14158917

申请日：2014-01-20

Applicant: International Business Machines Corporation

Inventor： Kai D. Feng ,  Wai-Kin Li ,  Ping-Chuan Wang ,  Zhijian J. Yang

IPC: H03K19/003 ,  H01L27/088 ,  H01L23/58 ,  H01L21/8234 ,  H01L21/266 ,  H01L21/31 ,  H01L27/02

CPC classification number: H03K19/00315 ,  H01L21/26513 ,  H01L21/823425 ,  H01L21/823493 ,  H01L23/544 ,  H01L23/57 ,  H01L27/0203 ,  H01L27/088 ,  H01L2223/54413 ,  H01L2223/5444 ,  H01L2924/0002 ,  H04L9/3278 ,  H01L2924/00

Abstract: A Physical Unclonable Function (PUF) semiconductor device includes a semiconductor substrate, and a well formed in the semiconductor substrate. The well includes a first region having a first concentration of ions, and at least one second region having a second concentration that is less than the first concentration. First and second FETs are formed on the well. The first and second FETs have a voltage threshold mismatch with respect to one another based on the first region and the at least one second region.

Abstract translation: 物理不可克隆功能（PUF）半导体器件包括半导体衬底和在半导体衬底中形成的阱。 阱包括具有第一离子浓度的第一区域和具有小于第一浓度的第二浓度的至少一个第二区域。 在井上形成第一和第二FET。 第一和第二FET基于第一区域和至少一个第二区域相对于彼此具有电压阈值失配。

公开(公告)号：US09059173B2

公开(公告)日：2015-06-16

申请号：US14508471

申请日：2014-10-07

Applicant: International Business Machines Corporation

Inventor： Ronald G. Filippi ,  John A. Fitzsimmons ,  Erdem Kaltalioglu ,  Ping-Chuan Wang ,  Lijuan Zhang

IPC: H01L29/00 ,  H01L23/525 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5256 ,  H01L21/76826 ,  H01L21/76834 ,  H01L21/76886 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electronic fuse structure having an Mx level including an Mx dielectric, a fuse line, an Mx cap dielectric above at least a portion of the Mx dielectric, and a modified portion of the Mx cap dielectric directly above at least a portion of the fuse line, where the modified portion of the Mx cap dielectric is chemically different from the remainder of the Mx cap dielectric, an Mx+1 level including an Mx+1 dielectric, a first Mx+1 metal, an Mx+1 cap dielectric above of the Mx+1 dielectric and the first Mx+1 metal, where the Mx+1 level is above the Mx level, and a first via electrically connecting the fuse line to the first Mx+1 metal.

Abstract translation: 一种具有Mx级的电子熔丝结构，其包括在Mx电介质的至少一部分上方的Mx电介质，熔丝线，Mx帽电介质，以及直接位于熔丝线的至少一部分上方的Mx帽电介质的改质部分 ，其中Mx帽电介质的改性部分在化学上不同于Mx帽电介质的其余部分，Mx + 1电平包括Mx + 1电介质，Mx + 1电极，Mx + 1金属，Mx + 1帽电介质 Mx + 1电介质和第一Mx + 1金属，其中Mx + 1电平高于Mx电平，以及第一通孔将熔丝线电连接到第一Mx + 1金属。

公开(公告)号：US09059051B2

公开(公告)日：2015-06-16

申请号：US13889374

申请日：2013-05-08

Applicant: International Business Machines Corporation

Inventor： Hanyi Ding ,  J. Edwin Hostetter, Jr. ,  Ping-Chuan Wang ,  Kimball M. Watson

IPC: H01L21/66

CPC classification number: H01L22/26 ,  H01L21/304 ,  H01L22/14 ,  H01L22/34

Abstract: A through-silicon via (TSV) capacitive test structure and method of determining TSV depth based on capacitance is disclosed. The TSV capacitive test structure is formed from a plurality of TSV bars that are evenly spaced. A first group of bars are electrically connected to form a first capacitor node, and a second group of bars is electrically connected to form a second capacitor node. The capacitance is measured, and a TSV depth is computed, prior to backside thinning. The computed TSV depth may then be fed to downstream grinding and/or polishing tools to control the backside thinning process such that the semiconductor wafer is thinned such that the backside is flush with the TSV.

Abstract translation: 公开了一种通过硅通孔（TSV）电容测试结构和基于电容确定TSV深度的方法。 TSV电容测试结构由均匀间隔的多个TSV条形成。 第一组电杆电连接以形成第一电容器节点，并且第二组电杆电连接以形成第二电容器节点。 测量电容，并在背面变薄之前计算TSV深度。 然后计算的TSV深度可以被馈送到下游研磨和/或抛光工具以控制背面变薄处理，使得半导体晶片变薄使得背面与TSV齐平。