公开(公告)号：US09799655B1

公开(公告)日：2017-10-24

申请号：US15137036

申请日：2016-04-25

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Xin Miao ,  Wenyu Xu ,  Chen Zhang

IPC: H01L21/00 ,  H01L21/338 ,  H01L21/337 ,  H01L21/8238 ,  H01L29/74 ,  H01L29/80 ,  H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L23/535

CPC classification number: H01L27/0924 ,  H01L21/6835 ,  H01L21/76895 ,  H01L21/823821 ,  H01L21/823885 ,  H01L21/84 ,  H01L22/22 ,  H01L23/50 ,  H01L23/5286 ,  H01L23/535 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/7827 ,  H01L29/785 ,  H01L2221/68359

Abstract: Various embodiments disclose a method for fabricating vertical transistors. In one embodiment, a structure is formed comprising at least a first substrate, an insulator layer on the substrate, a first doped layer on the insulator layer, at least one fin structure in contact with the doped layer, a dielectric layer surrounding a portion of the fin structure, a gate layer on the dielectric layer, a second doped layer in contact with the fin structure, a first contact area in contact with the second doped layer, and at least a first interconnect in contact with the first contact area. The structure is flipped bonded to a second substrate. The first substrate and the insulator layer are removed to expose the first doped layer. A second contact area is formed in contact with the first doped layer. At least a second interconnect is formed in contact with the second contact area.

公开(公告)号：US20170256655A1

公开(公告)日：2017-09-07

申请号：US15603945

申请日：2017-05-24

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Michael A. Guillorn ,  Isaac Lauer ,  Xin Miao

IPC: H01L29/786 ,  H01L21/02 ,  H01L21/311 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/78696 ,  H01L21/02236 ,  H01L21/31111 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66772 ,  H01L29/78654

Abstract: A method for fabricating a semiconductor device comprises forming a sacrificial layer of a first semiconductor material on a substrate, a layer of a second semiconductor material on the sacrificial layer, and a layer of a third semiconductor material on the layer of the second semiconductor material. Portions of the layer of the deposited material are removed to form a first nanowire arranged on the sacrificial fin and a second nanowire arranged on the first nanowire. An oxidizing process is performed that forms a first layer of oxide material on exposed portions of the second nanowire and a second layer of oxide material on exposed portions of the sacrificial fin, the first layer of oxide material having a first thickness and the second layer of oxide material having a second thickness, where the first thickness is less than the second thickness.

公开(公告)号：US09721897B1

公开(公告)日：2017-08-01

申请号：US15276985

申请日：2016-09-27

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Xin Miao ,  Peng Xu ,  Chen Zhang

IPC: H01L21/768 ,  H01L29/06 ,  H01L23/535 ,  H01L21/306 ,  H01L29/66

CPC classification number: H01L29/4991 ,  H01L21/02126 ,  H01L21/28247 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/7682 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656

Abstract: A method of fabricating a semiconductor transistor and the semiconductor transistor include a source region and a drain region within a substrate. The method includes forming a gate above the substrate, forming a source contact above the source region and a drain contact above the drain region, and forming air spacers within a dielectric between the gate and each of the source contact and the drain contact. Metal caps are formed on the source contact and the drain contact, and a gate cap is formed between the dielectric and at least a portion of a bottom surface of higher-level contacts, which are contacts formed above the source contact and the drain contact.

公开(公告)号：US09716158B1

公开(公告)日：2017-07-25

申请号：US15076362

申请日：2016-03-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Nicolas Jean Loubet ,  Xin Miao ,  Alexander Reznicek

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/764 ,  H01L29/49 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L23/535 ,  H01L23/532 ,  H01L21/768 ,  H01L29/06

CPC classification number: H01L29/4991 ,  H01L21/764 ,  H01L21/7682 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823475 ,  H01L23/53257 ,  H01L23/535 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L2221/1063

Abstract: Unfilled gaps are provided as spacers between gate stacks and electrically conductive source/drain contacts to reduce parasitic capacitance in CMOS structures. Sidewall spacers are removed partially or entirely from portions of the gate stacks and replaced by materials such as amorphous semiconductor materials. Source/drain contacts subsequently formed on source/drain regions adjoin the spacer replacement material. Selective removal of the spacer replacement material leaves unfilled gaps between the source/drain contacts and the gate stacks. The unfilled gaps are then sealed by a dielectric layer that leaves the gaps substantially unfilled.

公开(公告)号：US09716142B2

公开(公告)日：2017-07-25

申请号：US14880659

申请日：2015-10-12

Applicant: International Business Machines Corporation

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Juntao Li ,  Xin Miao

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L29/423 ,  H01L21/02 ,  H01L21/306 ,  H01L21/324 ,  H01L21/3105

CPC classification number: H01L21/3105 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/30608 ,  H01L21/324 ,  H01L29/0676 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L2029/7858

Abstract: Techniques for producing stacked SiGe nanowires using a condensation process without parasitic Ge nanowires as an undesired by-product. In one aspect, a method of forming SiGe nanowires includes the steps of: forming a stack of alternating Si and SiGe layers on a wafer; patterning fins in the stack; selectively thinning the SiGe layers in the fins such that the Si and SiGe layers give the fins an hourglass shape; burying the fins in an oxide material; and annealing the fins under conditions sufficient to diffuse Ge from the SiGe layers in the fins to the Si layers in the fins to form the SiGe nanowires. A FET device and method for formation thereof are also provided.

公开(公告)号：US09666693B1

公开(公告)日：2017-05-30

申请号：US15295130

申请日：2016-10-17

Applicant: International Business Machines Corporation

Inventor： Bruce B. Doris ,  Terence B. Hook ,  Xin Miao

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/417 ,  H01L29/06 ,  H01L29/786 ,  H01L29/66 ,  H01L21/306 ,  H01L21/311 ,  H01L29/08

CPC classification number: H01L29/6681 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/267 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7851 ,  H01L29/7853

Abstract: A method of making a semiconductor device includes forming a nanosheet stack including a first layer and a second layer; patterning a gate stack on the nanosheet stack; forming a first spacer along a sidewall of the gate stack; removing an endwall portion of the nanosheet stack that extends beyond the first spacer such that a portion of the second layer is exposed from a sidewall of the first spacer; depositing a second spacer along a sidewall of the first spacer; recessing the substrate beneath the second spacer to form an isolation region; depositing an oxide on the gate stack and within the isolation region and partially recessing the oxide; removing a portion of the second spacer such that the portion of the second layer is exposed; and growing an epitaxial layer on the portion of the second layer that is exposed to form a source/drain over the isolation region.

公开(公告)号：US09443977B1

公开(公告)日：2016-09-13

申请号：US14967732

申请日：2015-12-14

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Juntao Li ,  Xin Miao ,  Junli Wang

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/161 ,  H01L29/06 ,  H01L29/66 ,  H01L21/306 ,  H01L21/308 ,  H01L21/02 ,  H01L21/762 ,  H01L21/311 ,  H01L21/324

CPC classification number: H01L29/7848 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/31111 ,  H01L21/76224 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method for forming a semiconductor device comprises patterning and etching a fin in a semiconductor substrate, forming a gate stack over the fin, epitaxially growing a first semiconductor material on exposed portions of the fin, epitaxially growing a second semiconductor material on exposed portions of the first semiconductor material, and performing an etching process that removes exposed portions of the first semiconductor material and exposed portions of the second semiconductor material, the etching process is operative to remove portions of the first semiconductor material at a faster rate than the second semiconductor material such that a first cavity is formed adjacent to the fin.

公开(公告)号：US11908937B2

公开(公告)日：2024-02-20

申请号：US17376752

申请日：2021-07-15

Applicant: International Business Machines Corporation

Inventor： Xin Miao ,  Kangguo Cheng ,  Chen Zhang ,  Wenyu Xu

IPC: H01L29/78 ,  H01L29/66 ,  H10B10/00

CPC classification number: H01L29/7846 ,  H01L29/66553 ,  H01L29/785 ,  H01L2029/7858 ,  H10B10/12

Abstract: Vertical transport field-effect transistors are formed on active regions wherein the active regions each include a wrap-around metal silicide contact on vertically extending side walls of the active region. Such wrap-around contacts form self-aligned and reliable strapping for SRAM bottom nFET and pFET source/drain regions. Buried contacts of SRAM cells may be used to strap the wrap-around metal silicide contacts with the gates of inverters thereof. Wrap-around metal silicide contacts provide additional contacts for logic FETs and reduce parasitic bottom source/drain resistance.

公开(公告)号：US11881505B2

公开(公告)日：2024-01-23

申请号：US17198214

申请日：2021-03-10

Applicant: International Business Machines Corporation

Inventor： Choonghyun Lee ,  Xin Miao ,  Alexander Reznicek ,  Jingyun Zhang

IPC: H01L29/06 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/762 ,  H01L21/768 ,  H01L29/161 ,  H01L29/78 ,  H01L29/66 ,  H01L27/092

CPC classification number: H01L29/0649 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/76224 ,  H01L21/76832 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0665 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor structure includes a plurality of fins on a semiconductor substrate, the plurality of fins including an alternating sequence of a first nanosheet made of epitaxially grown silicon and a second nanosheet made of epitaxially grown silicon germanium, and a shallow trench isolation region within the semiconductor substrate adjacent to the plurality of fins. The shallow trench isolation region including a recess within the substrate filled with a first liner, a second liner directly above the first liner, a third liner directly above the second liner, and a dielectric material directly above the third liner. The first liner is made of a first oxide material, the third liner is made of a nitride material, and the second liner is made of a second oxide material that creates a dipole effect for neutralizing positive charges within the third liner and positive charges between the third liner and the first liner.

公开(公告)号：US11735658B2

公开(公告)日：2023-08-22

申请号：US16743637

申请日：2020-01-15

Applicant: International Business Machines Corporation

Inventor： Xin Miao ,  Chen Zhang ,  Kangguo Cheng ,  Wenyu Xu

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/306 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/207 ,  H01L29/66

CPC classification number: H01L29/7827 ,  H01L21/0262 ,  H01L21/02546 ,  H01L21/30621 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/207 ,  H01L29/66522 ,  H01L29/66666

Abstract: A method for manufacturing a semiconductor device includes forming a source layer on a semiconductor substrate, forming a channel layer on the source layer, and forming a drain layer on the channel layer. The source, channel and drain layers are patterned into at least one fin, and a cap layer is formed on a lower portion of the at least one fin. The lower portion of the at least one fin includes the source layer and part of the channel layer. The method further includes forming a gate structure comprising a gate dielectric layer and a gate conductor on the at least one fin and on the cap layer. The cap layer is positioned between the lower portion of the at least one fin and the gate dielectric layer.