公开(公告)号：US06780704B1

公开(公告)日：2004-08-24

申请号：US09452844

申请日：1999-12-03

Applicant: Ivo Raaijmakers ,  Suvi P. Haukka ,  Ernst H. A. Granneman

Inventor： Ivo Raaijmakers ,  Suvi P. Haukka ,  Ernst H. A. Granneman

IPC: H01L218242

CPC classification number: H01L28/40 ,  H01L21/02159 ,  H01L21/02178 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/02304 ,  H01L21/31604 ,  H01L21/3162 ,  H01L21/31691 ,  H01L27/10852 ,  H01L27/10861 ,  H01L28/84 ,  Y10T428/265

Abstract: Method and structures are provided for conformal capacitor dielectrics over textured silicon electrodes for integrated memory cells. Capacitor structures and first electrodes or plates are formed above or within semiconductor substrates. The first electrodes include hemispherical grain (HSG) silicon for increasing the capacitor plate surface area. The HSG topography is then exposed to alternating chemistries to form monolayers of a desired dielectric material. Exemplary process flows include alternately pulsed metal organic and oxygen source gases injected into a constant carrier flow. Self-terminated metal layers are thus reacted with oxygen. Near perfect step coverage allows minimal thickness for a capacitor dielectric, given leakage concerns for particular materials, thereby maximizing the capacitance for the memory cell and increasing cell reliability for a given memory cell design. Alternately pulsed chemistries are also provided for depositing top electrode materials with continuous coverage of capacitor dielectric, realizing the full capacitance benefits of the underlying textured morphology.

公开(公告)号：US06492283B2

公开(公告)日：2002-12-10

申请号：US09791167

申请日：2001-02-22

Applicant: Ivo Raaijmakers ,  Yong-Bae Kim ,  Marko Tuominen ,  Suvi P. Haukka

Inventor： Ivo Raaijmakers ,  Yong-Bae Kim ,  Marko Tuominen ,  Suvi P. Haukka

IPC: H01L2131

CPC classification number: H01L21/28194 ,  H01L21/02049 ,  H01L21/02052 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02299 ,  H01L21/02359 ,  H01L21/28167 ,  H01L21/28211 ,  H01L21/31662 ,  H01L29/517 ,  Y10S438/906

Abstract: A method is disclosed for forming an ultrathin oxide layer of uniform thickness. The method is particularly advantageous for producing uniformly thin interfacial oxides beneath materials of high dielectric permittivity, or uniformly thin passivation oxides. Hydrofluoric (HF) etching of a silicon surface, for example, is followed by termination of the silicon surface with ligands larger than H or F, particularly hydroxyl, alkoxy or carboxylic tails. The substrate is oxidized with the surface termination in place. The surface termination and relatively low temperatures moderate the rate of oxidation, such that a controllable thickness of oxide is formed. In some embodiments, the ligand termination is replaced with OH prior to further deposition. The deposition preferably includes alternating, self-limiting chemistries in an atomic layer deposition process, though any other suitable deposition process can be used. Two or more of the HF etching, surface termination, oxidation, hydroxyl replacement of the surface termination and deposition on the oxide can be conducted in situ.

Abstract translation: 公开了形成均匀厚度的超薄氧化物层的方法。 该方法特别有利于在高介电常数材料或均匀薄的钝化氧化物材料下制备均匀的薄界面氧化物。 例如，硅表面的氢氟酸（HF）蚀刻之后，用大于H或F的配体，特别是羟基，烷氧基或羧酸尾部的配位体终止硅表面。 衬底被氧化，表面终止就位。 表面终止和相对低的温度调节氧化速率，使得形成可控的氧化物厚度。 在一些实施方案中，在进一步沉积之前，将配体终止物用OH代替。 沉积优选地包括在原子层沉积工艺中的交替的自限制化学，尽管可以使用任何其它合适的沉积工艺。 HF蚀刻，表面终止，氧化，羟基取代表面终止和沉积在氧化物上的两个或多个可以原位进行。

公开(公告)号：US06284048B1

公开(公告)日：2001-09-04

申请号：US09596628

申请日：2000-06-19

Applicant: Franciscus Bernardus Maria Van Bilsen ,  Jason Mathew Layton ,  Ivo Raaijmakers

Inventor： Franciscus Bernardus Maria Van Bilsen ,  Jason Mathew Layton ,  Ivo Raaijmakers

IPC: C23C1600

CPC classification number: C30B29/06 ,  C30B25/10

Abstract: A method is provided for treating wafers on a low mass support. The method includes mounting a temperature sensor in proximity to the wafer, which is supported on the low mass support, such that the sensor is only loosely thermally coupled to the wafer. A temperature controller is programmed to critically tune the wafer temperature in a temperature ramp, though the controller directly controls the sensor temperature. A wafer treatment, such as epitaxial silicon deposition, is started before the sensor temperature has stabilized. Accordingly, significant time is saved for the treatment process, and wafer throughput improved.

Abstract translation: 提供了一种用于在低质量支撑件上处理晶片的方法。 该方法包括将温度传感器安装在靠近晶片的位置，该温度传感器被支撑在低质量支架上，使得传感器仅松散地热耦合到晶片。 温度控制器被编程为在温度斜坡中严格调整晶片温度，尽管控制器直接控制传感器温度。 在传感器温度稳定之前开始诸如外延硅沉积的晶片处理。 因此，为处理过程节省了大量时间，并提高了晶片生产能力。

公开(公告)号：US06232196B1

公开(公告)日：2001-05-15

申请号：US09264167

申请日：1999-03-05

Applicant: Ivo Raaijmakers ,  Christopher François Lilian Pomarède ,  Cornelius Alexander van der Jengd ,  Alexander Gschwandtner ,  Andreas Grassl

Inventor： Ivo Raaijmakers ,  Christopher François Lilian Pomarède ,  Cornelius Alexander van der Jengd ,  Alexander Gschwandtner ,  Andreas Grassl

IPC: H01L2120

CPC classification number: C23C16/45504 ,  C23C16/045 ,  C23C16/24 ,  C23C16/455 ,  C23C16/45502 ,  C23C16/45591 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/0262 ,  H01L21/28525 ,  H01L21/28556 ,  H01L21/76877 ,  H01L29/66181 ,  H01L29/78

Abstract: A method is disclosed for depositing silicon with high deposition rates and good step coverage. The process is performed at high pressures, including close to atmospheric pressures, at temperatures of greater than about 650° C. Silane and hydrogen are flowed over a substrate in a single-wafer chamber. Advantageously, the process maintains good step coverage and high deposition rates (e.g., greater that 50 nn/min) even when dopant gases are added to the process, resulting in commercially practicable rates of deposition for conductive silicon. Despite the high deposition rates, step coverage is sufficient to deposit polysilicon into extremely deep trenches and vias with aspect ratios as high as 40:1, filling such structures without forming voids or keyholes.

Abstract translation: 公开了一种用于沉积具有高沉积速率和良好的台阶覆盖率的硅的方法。 该方法在大于约650℃的温度下在高压（包括接近大气压）下进行。硅烷和氢气在单晶片室中流过衬底。 有利的是，即使将掺杂剂气体加入到该方法中，该方法保持良好的阶梯覆盖率和高的沉积速率（例如，大于50nn / min），从而导致商业上可行的导电硅沉积速率。 尽管沉积速率高，但步长覆盖足以将多晶硅沉积到具有高达40:1的纵横比的极深沟槽和通孔中，填充这种结构而不形成空隙或键孔。

公开(公告)号：US6121061A

公开(公告)日：2000-09-19

申请号：US184491

申请日：1998-11-02

Applicant: Franciscus Bernardus Maria Van Bilsen ,  Jason Mathew Layton ,  Ivo Raaijmakers

Inventor： Franciscus Bernardus Maria Van Bilsen ,  Jason Mathew Layton ,  Ivo Raaijmakers

IPC: H01L21/66 ,  C30B25/02 ,  C30B25/10 ,  H01L21/205 ,  H01L21/26 ,  H01L21/683 ,  G01R31/26

CPC classification number: C30B29/06 ,  C30B25/10

Abstract: A method is provided for treating wafers on a low mass support. The method includes mounting a temperature sensor in proximity to the wafer, which is supported on the low mass support, such that the sensor is only loosely thermally coupled to the wafer. A temperature controller is programmed to critically tune the wafer temperature in a temperature ramp, though the controller directly controls the sensor temperature. A wafer treatment, such as epitaxial silicon deposition, is started before the sensor temperature has stabilized. Accordingly, significant time is saved for the treatment process, and wafer throughput improved.

Abstract translation: 提供了一种用于在低质量支撑件上处理晶片的方法。 该方法包括将温度传感器安装在靠近晶片的位置，该温度传感器被支撑在低质量支架上，使得传感器仅松散地热耦合到晶片。 温度控制器被编程为在温度斜坡中严格调整晶片温度，尽管控制器直接控制传感器温度。 在传感器温度稳定之前开始诸如外延硅沉积的晶片处理。 因此，为处理过程节省了大量时间，并提高了晶片生产能力。

公开(公告)号：US6108937A

公开(公告)日：2000-08-29

申请号：US150986

申请日：1998-09-10

Applicant: Ivo Raaijmakers

Inventor： Ivo Raaijmakers

IPC: C23C16/44 ,  C23C16/54 ,  C23C16/56 ,  C30B25/10 ,  H01L21/00 ,  H01L21/205 ,  F26B7/00

CPC classification number: H01L21/67109 ,  C23C16/54 ,  C23C16/56 ,  C30B25/10

Abstract: Methods and apparatuses are provided for cooling semiconductor substrates prior to handling. In one embodiment, a substrate and support structure combination is lifted after high temperature processing to a cold wall of a thermal processing chamber, which acts as a heat sink. Conductive heat transfer across a small gap from the substrate to the heat sink speeds wafer cooling prior to handling the wafer (e.g., with a robot). In another embodiment, a separate plate is kept cool within a pocket during processing, and is moved close to the substrate and support after processing. In yet another embodiment, a cooling station between a processing chamber and a storage cassette includes two movable cold plates, which are movable to positions closely spaced on either side of the wafer.

Abstract translation: 提供了用于在处理之前冷却半导体衬底的方法和装置。 在一个实施例中，将衬底和支撑结构组合在高温处理之后提升到用作散热器的热处理室的冷壁。 在从基板到散热片的小间隙处的导电热传递在处理晶片（例如，使用机器人）之前加速晶片冷却。 在另一个实施例中，单独的板在处理期间保持在袋内冷却，并且在处理之后移动靠近基板并支撑。 在另一个实施例中，处理室和存储盒之间的冷却站包括两个可移动的冷板，其可移动到在晶片的任一侧上紧密间隔开的位置。

公开(公告)号：US6013159A

公开(公告)日：2000-01-11

申请号：US971246

申请日：1997-11-16

Applicant: Bret W. Adams ,  Ivo Raaijmakers

Inventor： Bret W. Adams ,  Ivo Raaijmakers

IPC: C23C14/56 ,  H01J37/34 ,  C23C14/00 ,  C23C14/34

CPC classification number: H01J37/3455 ,  C23C14/564 ,  H01J37/3408

Abstract: A plasma sputtering reactor in which a magnet is linearly scanned over the back of the sputtering target to enhance the sputtering. The magnet's linear scan is extended to beyond the wafer processing area. When the magnet reaches that point, conditions are changed within the reactor to cause particles otherwise trapped by the magnet to fall into an area of the reactor where they do not fall on the substrate being processed. The changed conditions may include extinguishing the plasma, reducing or reversing the target voltage, positively charging walls of the trap area, or pulsing gas through the plasma. Also, according to the invention, the plasma is ignited with the magnet positioned over the trap area so that particles generated in the ignition process are not immediately deposited on the wafer or the walls of the processing area, and they tend to stay in the trap area.

Abstract translation: 一种等离子溅射反应器，其中磁体在溅射靶的背面线性扫描以增强溅射。 磁体的线性扫描扩展到晶片处理区域之外。 当磁体达到该点时，反应器内的条件被改变，导致由磁体捕获的颗粒落入反应器的不被落在被处理的基板上的区域中。 改变的条件可能包括熄灭等离子体，减少或反转目标电压，积极地填充陷阱区域的壁或脉冲气体通过等离子体。 此外，根据本发明，等离子体被定位在捕获区域上方的磁体点燃，使得在点火过程中产生的颗粒不会立即沉积在晶片或处理区域的壁上，并且它们倾向于停留在阱中 区。

公开(公告)号：US5989999A

公开(公告)日：1999-11-23

申请号：US939914

申请日：1997-09-26

Applicant: Timothy E. Levine ,  Ling Chen ,  Mei Chang ,  Roderick C. Mosely ,  Karl A. Littau ,  Ivo Raaijmakers

Inventor： Timothy E. Levine ,  Ling Chen ,  Mei Chang ,  Roderick C. Mosely ,  Karl A. Littau ,  Ivo Raaijmakers

IPC: C23C16/34 ,  C23C16/458 ,  C23C16/48 ,  C23C16/509 ,  C23C16/56 ,  H01L21/768 ,  H01L21/4763

CPC classification number: H01L21/76864 ,  C23C16/34 ,  C23C16/4581 ,  C23C16/4586 ,  C23C16/481 ,  C23C16/5096 ,  C23C16/56 ,  H01J37/32174 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76862

Abstract: The construction of a film on a wafer, which is placed in a processing chamber, may be carried out through the following steps. A layer (film) of tantalum nitride material is deposited on the wafer. Next, the layer of tantalum nitride material is annealed. The deposition and annealing may both be accomplished in the same chamber, without need for removing the wafer from the chamber until both steps are completed.

Abstract translation: 放置在处理室中的晶片上的膜的构造可以通过以下步骤进行。 在晶片上沉积氮化钽材料层（膜）。 接下来，对氮化钽层进行退火。 沉积和退火都可以在相同的室中完成，而不需要从腔室中移除晶片，直到完成两个步骤。

公开(公告)号：US5827408A

公开(公告)日：1998-10-27

申请号：US693823

申请日：1996-07-26

Applicant: Ivo Raaijmakers

Inventor： Ivo Raaijmakers

IPC: C23C14/04 ,  C23C14/34

CPC classification number: C23C14/345 ,  C23C14/046 ,  C23C14/34 ,  H01J37/3447

Abstract: A sputtering process is chemically enhanced to improve conformality of the sputter deposited film by adding a flow of a halogen-containing etch gas during sputter deposition. A reducing gas can be added near the substrate to aid in the deposition reaction. A physical vapor deposition chamber is modified to provide a reducing gas inlet near the substrate.

Abstract translation: 通过在溅射沉积期间添加含卤素蚀刻气体的流动，化学增强溅射工艺以改善溅射沉积膜的共形性。 可以在基底附近添加还原气体以帮助沉积反应。 改变物理气相沉积室以在基底附近提供还原气体入口。

公开(公告)号：US20110269310A1

公开(公告)日：2011-11-03

申请号：US13084341

申请日：2011-04-11

Applicant: Ivo Raaijmakers

Inventor： Ivo Raaijmakers

IPC: H01L21/28 ,  B82Y40/00

CPC classification number: H01L21/76823 ,  C23C16/405 ,  C23C16/56 ,  H01L21/28518 ,  H01L21/28562 ,  H01L29/665 ,  H01L29/66568

Abstract: A method of self-aligned silicidation on structures having high aspect ratios involves depositing a metal oxide film using atomic layer deposition (ALD) and converting the metal oxide film to metal film in order to obtain uniform step coverage. The substrate is then annealed such that the metal in regions directly overlying the patterned and exposed silicon reacts with the silicon to form uniform metal silicide at the desired locations.

Abstract translation: 在具有高纵横比的结构上的自对准硅化物的方法包括使用原子层沉积（ALD）沉积金属氧化物膜并将金属氧化物膜转化为金属膜以获得均匀的台阶覆盖。 然后将衬底退火，使得直接覆盖图案化和暴露的硅的区域中的金属与硅反应，以在期望的位置形成均匀的金属硅化物。