公开(公告)号：US07442993B2

公开(公告)日：2008-10-28

申请号：US11293774

申请日：2005-12-02

申请人： Stephen W. Bedell ,  Anthony G. Domenicucci ,  Keith E. Fogel ,  Effendi Leobandung ,  Devendra K. Sadana

发明人： Stephen W. Bedell ,  Anthony G. Domenicucci ,  Keith E. Fogel ,  Effendi Leobandung ,  Devendra K. Sadana

IPC分类号： H01L31/392

CPC分类号： H01L29/78696 ,  H01L21/0237 ,  H01L21/02439 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02521 ,  H01L21/02667 ,  H01L21/02694 ,  H01L21/76251 ,  H01L29/7842

摘要： A method of forming a semiconductor structure comprising a first strained semiconductor layer over an insulating layer is provided in which the first strained semiconductor layer is relatively thin (less than about 500 Å) and has a low defect density (stacking faults and threading defects). The method of the present invention begins with forming a stress-providing layer, such a SiGe alloy layer over a structure comprising a first semiconductor layer that is located atop an insulating layer. The stress-providing layer and the first semiconductor layer are then patterned into at least one island and thereafter the structure containing the at least one island is heated to a temperature that causes strain transfer from the stress-providing layer to the first semiconductor layer. After strain transfer, the stress-providing layer is removed from the structure to form a first strained semiconductor island layer directly atop said insulating layer.

摘要翻译： 提供了一种在绝缘层上形成包括第一应变半导体层的半导体结构的方法，其中第一应变半导体层相对较薄（小于约）并且具有低缺陷密度（堆垛层错和穿线缺陷）。 本发明的方法开始于在包括位于绝缘层顶部的第一半导体层的结构上形成应力提供层，例如SiGe合金层。 然后将应力提供层和第一半导体层图案化成至少一个岛，然后将含有至少一个岛的结构加热到使得应力转移从应力提供层到第一半导体层的温度。 在应变转移之后，将应力提供层从结构上去除，以形成直接位于所述绝缘层顶部的第一应变半导体岛层。

公开(公告)号：US07317226B2

公开(公告)日：2008-01-08

申请号：US10993270

申请日：2004-11-19

申请人： Keith E. Fogel ,  Mark C. Hakey ,  Steven J. Holmes ,  Devendra K. Sadana ,  Ghavam G. Shahidi

发明人： Keith E. Fogel ,  Mark C. Hakey ,  Steven J. Holmes ,  Devendra K. Sadana ,  Ghavam G. Shahidi

IPC分类号： H01L27/01

CPC分类号： H01L21/76243 ,  H01L21/26506 ,  H01L21/76267 ,  Y10T428/12674 ,  Y10T428/12681

摘要： Methods for forming a patterned SOI region in a Si-containing substrate is provided which has geometries of about 0.25 μm or less. Specifically, one method includes the steps of: forming a patterned dielectric mask on a surface of a Si-containing substrate, wherein the patterned dielectric mask includes vertical edges that define boundaries for at least one opening which exposes a portion of the Si-containing substrate; implanting oxygen ions through the at least one opening removing the mask and forming a Si layer on at least the exposed surfaces of the Si-containing substrate; and annealing at a temperature of about 1250° C. or above and in an oxidizing ambient so as to form at least one discrete buried oxide region in the Si-containing substrate. In one embodiment, the mask is not removed until after the annealing step; and in another embodiment, the Si-containing layer is formed after annealing and mask removal.

摘要翻译： 提供了在含Si衬底中形成图案化SOI区的方法，其具有约0.25μm或更小的几何形状。 具体而言，一种方法包括以下步骤：在含Si衬底的表面上形成图案化电介质掩模，其中，图案化电介质掩模包括垂直边缘，其限定至少一个露出一部分含Si衬底的开口的边界 ; 通过所述至少一个开口注入氧离子，去除所述掩模并在至少所述含Si衬底的暴露表面上形成Si层; 并在约1250℃或更高的温度下和在氧化环境中进行退火，以便在含Si衬底中形成至少一个离散的掩埋氧化物区域。 在一个实施例中，直到退火步骤之后，掩模才被去除; 并且在另一个实施方案中，在退火和掩模去除之后形成含Si层。

公开(公告)号：US07304328B2

公开(公告)日：2007-12-04

申请号：US10982411

申请日：2004-11-05

申请人： Stephen W. Bedell ,  Keith E. Fogel ,  Devendra K. Sadana

发明人： Stephen W. Bedell ,  Keith E. Fogel ,  Devendra K. Sadana

IPC分类号： H01L21/336

CPC分类号： H01L21/76243 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02664 ,  Y10S438/933

摘要： A method of forming a relaxed SiGe-on-insulator substrate having enhanced relaxation, significantly lower defect density and improved surface quality is provided. The method includes forming a SiGe alloy layer on a surface of a first single crystal Si layer. The first single crystal Si layer has an interface with an underlying barrier layer that is resistant to Ge diffusion. Next, ions that are capable of forming defects that allow mechanical decoupling at or near said interface are implanted into the structure and thereafter the structure including the implanted ions is subjected to a heating step which permits interdiffusion of Ge throughout the first single crystal Si layer and the SiGe layer to form a substantially relaxed, single crystal and homogeneous SiGe layer atop the barrier layer. SiGe-on-insulator substrates having the improved properties as well as heterostructures containing the same are also provided.

摘要翻译： 提供了一种形成松弛的绝缘体上硅衬底的方法，其具有增强的松弛，显着降低缺陷密度和改进的表面质量。 该方法包括在第一单晶Si层的表面上形成SiGe合金层。 第一单晶硅层具有与Ge扩散耐受的下层阻挡层的界面。 接下来，能够形成允许在界面处或附近机械解耦的缺陷的离子被注入到结构中，此后包括注入的离子的结构经受加热步骤，其允许Ge贯穿整个第一单晶Si层和 SiGe层，以形成在阻挡层顶上基本上松弛的单晶和均匀的SiGe层。 还提供了具有改进性能的绝缘体上硅衬底以及含有其的异质结构。

公开(公告)号：US06946373B2

公开(公告)日：2005-09-20

申请号：US10300189

申请日：2002-11-20

申请人： Paul D. Agnello ,  Stephen W. Bedell ,  Robert H. Dennard ,  Anthony G. Domenicucci ,  Keith E. Fogel ,  Devendra K. Sadana

发明人： Paul D. Agnello ,  Stephen W. Bedell ,  Robert H. Dennard ,  Anthony G. Domenicucci ,  Keith E. Fogel ,  Devendra K. Sadana

IPC分类号： C30B25/02 ,  C30B29/52 ,  H01L21/20 ,  H01L21/205 ,  H01L21/324 ,  H01L21/337 ,  H01L21/84 ,  H01L21/477

CPC分类号： H01L21/324 ,  C30B25/02 ,  C30B29/52 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/7624 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/66893 ,  H01L29/78603

摘要： Thermal mixing methods of forming a substantially relaxed and low-defect SGOI substrate material are provided. The methods include a patterning step which is used to form a structure containing at least SiGe islands formed atop a Ge resistant diffusion barrier layer. Patterning of the SiGe layer into islands changes the local forces acting at each of the island edges in such a way so that the relaxation force is greater than the forces that oppose relaxation. The absence of restoring forces at the edges of the patterned layers allows the final SiGe film to relax further than it would if the film was continuous.

摘要翻译： 提供形成基本上松弛和低缺陷的SGOI基底材料的热混合方法。 所述方法包括图形化步骤，其用于形成至少包含形成在Ge抗蚀扩散阻挡层顶上的SiGe岛的结构。 将SiGe层图案化成岛以这样的方式改变作用在每个岛边缘处的局部力，使得松弛力大于抵抗放松的力。 在图案化层的边缘处没有恢复力允许最终的SiGe膜比如果膜是连续的那样进一步松弛。

公开(公告)号：US06825102B1

公开(公告)日：2004-11-30

申请号：US10664714

申请日：2003-09-18

申请人： Stephen W. Bedell ,  Keith E. Fogel ,  Shreesh Narasimha ,  Devendra K. Sadana

发明人： Stephen W. Bedell ,  Keith E. Fogel ,  Shreesh Narasimha ,  Devendra K. Sadana

IPC分类号： H01L21263

CPC分类号： H01L21/02667 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/2022 ,  Y10S438/933

摘要： A method in which a defective semiconductor crystal material is subjected to an amorphization step followed by a thermal treatment step is provided. The amorphization step amorphizes, partially or completely, a region, including the surface region, of a defective semiconductor crystal material. A thermal treatment step is next performed so as to recrystallize the amorphized region of the defective semiconductor crystal material. The recrystallization is achieved in the present invention by solid-phase crystal regrowth from the non-amorphized region of the defective semiconductor crystal material.

摘要翻译： 提供一种方法，其中对缺陷半导体晶体材料进行非晶化步骤之后进行热处理步骤。 非晶化步骤使部分地或完全地形成缺陷半导体晶体材料的区域，包括表面区域。 接下来进行热处理步骤，以便使缺陷半导体晶体材料的非晶化区域再结晶。 通过从缺陷半导体晶体材料的非非晶化区域的固相晶体再生长，在本发明中实现了重结晶。

公开(公告)号：US09373741B2

公开(公告)日：2016-06-21

申请号：US13586138

申请日：2012-08-15

申请人： Keith E. Fogel ,  Bahman Hekmatshoartabari ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

发明人： Keith E. Fogel ,  Bahman Hekmatshoartabari ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC分类号： H01L31/105 ,  H01L31/078 ,  H01L31/0725 ,  H01L31/0352 ,  H01L31/0745 ,  H01L31/076

CPC分类号： H01L31/078 ,  H01L31/035227 ,  H01L31/035281 ,  H01L31/0725 ,  H01L31/0745 ,  H01L31/076 ,  H01L31/1824 ,  H01L31/1884 ,  H01L31/20 ,  Y02E10/548

摘要： A photovoltaic device that includes an upper cell that absorbs a first range of wavelengths of light and a bottom cell that absorbs a second range of wavelengths of light. The bottom cell includes a heterojunction comprising a crystalline germanium containing (Ge) layer. At least one surface of the crystalline germanium (Ge) containing layer is in contact with a silicon (Si) containing layer having a larger band gap than the crystalline (Ge) containing layer.

摘要翻译： 一种光电器件，其包括吸收光的第一波长范围的上电池和吸收第二波长波长的底电池。 底部电池包括含有结晶含锗（Ge）层的异质结。 含结晶锗（Ge）层的至少一个表面与含有结晶（Ge）层的带隙较大的含硅（Si）层接触。

公开(公告)号：US09079269B2

公开(公告)日：2015-07-14

申请号：US13302427

申请日：2011-11-22

申请人： Stephen W. Bedell ,  Cheng-Wei Cheng ,  Keith E. Fogel ,  Devendra K. Sadana ,  Katherine L. Saenger ,  Norma E. Sosa Cortes ,  Ning Li ,  Ibrahim Alhomoudi

发明人： Stephen W. Bedell ,  Cheng-Wei Cheng ,  Keith E. Fogel ,  Devendra K. Sadana ,  Katherine L. Saenger ,  Norma E. Sosa Cortes ,  Ning Li ,  Ibrahim Alhomoudi

IPC分类号： B23K26/00 ,  H01L21/304 ,  B23K26/06 ,  B23K26/36 ,  B23K26/40

CPC分类号： H01L21/268 ,  B23K26/0624 ,  B23K26/364 ,  B23K26/40 ,  B23K2103/50 ,  H01L21/31127 ,  H01L21/32131 ,  H01L21/6835 ,  H01L2221/68327

摘要： Laser ablation can be used to form a trench within at least a blanket layer of a stressor layer that is atop a base substrate. A non-ablated portion of the stressor layer has an edge that defines the edge of the material layer region to be spalled. Laser ablation can also be used to form a trench within a blanket material stack including at least a plating seed layer. A stressor layer is formed on the non-ablated portions of the material stack and one portion of the stressor layer has an edge that defines the edge of the material layer region to be spalled. Laser ablation can be further used to form a trench that extends through a blanket stressor layer and into the base substrate itself. The trench has an edge that defines the edge of the material layer region to be spalled.

摘要翻译： 可以使用激光烧蚀在至少基底衬底顶部的应力层的至少一层覆盖层内形成沟槽。 应力层的非烧蚀部分具有限定要剥离的材料层区域的边缘的边缘。 激光烧蚀还可用于在包括至少镀覆种子层的覆盖材料堆叠内形成沟槽。 在材料堆叠的非烧蚀部分上形成应力层，应力层的一部分具有限定要剥离的材料层区域的边缘的边缘。 可以进一步使用激光烧蚀来形成延伸穿过覆盖应力层并进入基底本身的沟槽。 沟槽具有限定要剥离的材料层区域的边缘的边缘。

公开(公告)号：US08936961B2

公开(公告)日：2015-01-20

申请号：US13481795

申请日：2012-05-26

申请人： Stephen W. Bedell ,  Keith E. Fogel ,  Bahman Hekmatshoartabari ,  Paul A. Lauro ,  Ning Li ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

发明人： Stephen W. Bedell ,  Keith E. Fogel ,  Bahman Hekmatshoartabari ,  Paul A. Lauro ,  Ning Li ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC分类号： H01L21/00

CPC分类号： H01L31/0684 ,  H01L21/02002 ,  H01L31/1896 ,  Y02E10/547

摘要： A stressor layer used in a controlled spalling method is removed through the use of a cleave layer that can be fractured or dissolved. The cleave layer is formed between a host semiconductor substrate and the metal stressor layer. A controlled spalling process separates a relatively thin residual host substrate layer from the host substrate. Following attachment of a handle substrate to the residual substrate layer or other layers subsequently formed thereon, the cleave layer is dissolved or otherwise compromised to facilitate removal of the stressor layer. Such removal allows the fabrication of a bifacial solar cell.

摘要翻译： 以受控剥落方式使用的应力层通过使用可以断裂或溶解的裂开层去除。 在主体半导体衬底和金属应力层之间形成切割层。 受控的剥落过程将相对薄的残余主体衬底层与主体衬底分离。 在将手柄衬底附接到残留衬底层或随后在其上形成的其它层之后，解理层被溶解或以其他方式受到损害以便于去除应力层。 这种去除允许制造双面太阳能电池。

公开(公告)号：US08878055B2

公开(公告)日：2014-11-04

申请号：US12852991

申请日：2010-08-09

申请人： Keith E. Fogel ,  William S. Graham ,  Jeehwan Kim ,  Harold J. Hovel ,  Devendra K. Sadana ,  Katherine L. Saenger

发明人： Keith E. Fogel ,  William S. Graham ,  Jeehwan Kim ,  Harold J. Hovel ,  Devendra K. Sadana ,  Katherine L. Saenger

IPC分类号： H01L31/00 ,  H01L31/052 ,  H01L31/0236 ,  H01L31/0352

CPC分类号： H01L31/0527 ,  H01L31/02366 ,  H01L31/03529 ,  H01L31/056 ,  Y02E10/52

摘要： A photovoltaic device and method include a substrate layer having a plurality of structures including peaks and troughs formed therein. A continuous photovoltaic stack is conformally formed over the substrate layer and extends over the peaks and troughs. The photovoltaic stack has a thickness of less than one micron and is configured to transduce incident radiation into current flow.

摘要翻译： 光电器件和方法包括具有多个结构的衬底层，包括形成在其中的峰和谷。 连续的光伏堆叠保形地形成在衬底层上并且延伸超过峰和谷。 光伏堆叠具有小于1微米的厚度，并且被配置为将入射辐射转换成电流。

公开(公告)号：US08866003B2

公开(公告)日：2014-10-21

申请号：US13599591

申请日：2012-08-30

申请人： Ahmed Abou-Kandil ,  Keith E. Fogel ,  Jee H. Kim ,  Mohamed Saad ,  Devendra K. Sadana

发明人： Ahmed Abou-Kandil ,  Keith E. Fogel ,  Jee H. Kim ,  Mohamed Saad ,  Devendra K. Sadana

IPC分类号： H01L31/0288 ,  H01L31/18 ,  H01L31/0368 ,  H01L31/075 ,  H01L31/0224 ,  H01L31/0376 ,  H01L31/0392

CPC分类号： H01L31/075 ,  H01L31/022466 ,  H01L31/03685 ,  H01L31/03687 ,  H01L31/03762 ,  H01L31/03921 ,  H01L31/1816 ,  H01L31/1824 ,  Y02E10/545 ,  Y02E10/548 ,  Y02P70/521

摘要： A p-doped semiconductor layer of a photovoltaic device is formed employing an inert gas within a carrier gas. The presence of the inert gas within the carrier gas increases free hole density within the p-doped semiconductor layer. This decreases the Schottky barrier at an interface with a transparent conductive material layer, thereby significantly reducing the series resistance of the photovoltaic device. The reduction of the series resistance increases the open-circuit voltage, the fill factor, and the efficiency of the photovoltaic device. This effect is more prominent if the p-doped semiconductor layer is also doped with carbon, and has a band gap greater than 1.85V. The p-doped semiconductor material of the p-doped semiconductor layer can be hydrogenated if the carrier gas includes a mix of H2 and the inert gas.

摘要翻译： 使用载气内的惰性气体形成光伏器件的p掺杂半导体层。 载气内的惰性气体的存在增加了p掺杂半导体层内的自由空穴密度。 这降低了在与透明导电材料层的界面处的肖特基势垒，从而显着降低了光伏器件的串联电阻。 串联电阻的降低增加了光伏器件的开路电压，填充因子和效率。 如果p掺杂半导体层也掺杂有碳，并且具有大于1.85V的带隙，则该效果更加突出。 如果载气包括H 2和惰性气体的混合物，则p掺杂半导体层的p掺杂半导体材料可以被氢化。