公开(公告)号：US08389414B2

公开(公告)日：2013-03-05

申请号：US13026651

申请日：2011-02-14

申请人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Hideya Murai ,  Takuo Funaya ,  Kentaro Mori ,  Takehiko Maeda ,  Hirokazu Honda ,  Kenta Ogawa ,  Jun Tsukano

发明人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Hideya Murai ,  Takuo Funaya ,  Kentaro Mori ,  Takehiko Maeda ,  Hirokazu Honda ,  Kenta Ogawa ,  Jun Tsukano

IPC分类号： H01L21/311

CPC分类号： H05K3/205 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/563 ,  H01L23/498 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48472 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/181 ,  H01L2924/19041 ,  H05K3/244 ,  H05K3/423 ,  H05K2201/0338 ,  H05K2201/098 ,  H05K2201/09845 ,  H05K2203/0376 ,  H05K2203/0384 ,  H05K2203/0733 ,  H05K2203/1476 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/45015 ,  H01L2924/207

摘要： A wiring board has an insulating layer, a plurality of wiring layers formed in such a way as to be insulated from each other by the insulating layer, and a plurality of vias formed in the insulating layer to connect the wiring layers. Of the wiring layers, a surface wiring layer formed in one surface of the insulating layer include a first metal film exposed from the one surface and a second metal film embedded in the insulating layer and stacked on the first metal film. Edges of the first metal film project from edges of the second metal film in the direction in which the second metal film spreads. By designing the shape of the wiring layers embedded in the insulating layer in this manner, it is possible to obtain a highly reliable wiring board that can be effectively prevented from side etching in the manufacturing process and can adapt to miniaturization and highly dense packaging of wires.

摘要翻译： 布线基板具有绝缘层，多个布线层以通过绝缘层彼此绝缘的方式形成，以及形成在绝缘层中以连接布线层的多个通孔。 在布线层中，形成在绝缘层的一个表面上的表面布线层包括从一个表面露出的第一金属膜和嵌入在绝缘层中并叠放在第一金属膜上的第二金属膜。 第一金属膜的边缘沿着第二金属膜扩展的方向从第二金属膜的边缘突出。 通过以这种方式设计嵌入在绝缘层中的布线层的形状，可以获得在制造过程中可以有效地防止侧蚀刻的高可靠性布线板，并且可以适应电线的小型化和高密度封装 。

公开(公告)号：US20130050967A1

公开(公告)日：2013-02-28

申请号：US13634088

申请日：2011-01-19

申请人： Daisuke Ohshima ,  Katsumi Kikuchi ,  Yoshiki Nakashima ,  Kentaro Mori ,  Shintaro Yamamichi

发明人： Daisuke Ohshima ,  Katsumi Kikuchi ,  Yoshiki Nakashima ,  Kentaro Mori ,  Shintaro Yamamichi

IPC分类号： H05K1/18

CPC分类号： H01L23/5389 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/24227 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/18162 ,  H01L2924/3511 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/10416 ,  H01L2924/00

摘要： An object of the present invention is to provide a functional device-embedded substrate that can be thinned and suppress occurrence of warpage. The present invention provides a functional device-embedded substrate including at least a functional device including an electrode terminal, and a covering insulating layer covering at least an electrode terminal surface and a side surface of the functional device, the functional device-embedded substrate including a first pillar structure around the functional device inside the covering insulating layer, the first pillar structure including a material having a thermal expansion coefficient between thermal expansion coefficients of the functional device and the covering insulating layer, wherein the first pillar structure is arranged at a position where a shortest distance from a side surface of the functional device to a side surface of the first pillar structure is smaller than a thickness of the functional device.

摘要翻译： 本发明的目的是提供一种能够变薄并抑制翘曲发生的功能性器件嵌入式基板。 本发明提供一种功能性器件嵌入式基板，其至少包括具有电极端子的功能元件和覆盖所述功能元件的至少电极端子面和侧面的覆盖绝缘层，所述功能元件嵌入型基板包括 第一柱结构包括在功能元件的热膨胀系数与覆盖绝缘层之间具有热膨胀系数的材料的第一柱结构，其中第一柱结构布置在第一柱结构的位置， 从功能元件的侧面到第一柱状结构的侧面的最短距离小于功能元件的厚度。

公开(公告)号：US20130026632A1

公开(公告)日：2013-01-31

申请号：US13639735

申请日：2011-02-22

申请人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Hideya Murai ,  Kentaro Mori ,  Yoshiki Nakashima

发明人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Hideya Murai ,  Kentaro Mori ,  Yoshiki Nakashima

IPC分类号： H01L23/48

CPC分类号： H05K1/185 ,  H01L21/6835 ,  H01L23/481 ,  H01L23/50 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/83 ,  H01L2221/68345 ,  H01L2223/6677 ,  H01L2224/04105 ,  H01L2224/24225 ,  H01L2224/24226 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/73267 ,  H01L2224/83 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01088 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/0781 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/19041 ,  H05K1/0271 ,  H05K1/186 ,  H05K3/4602 ,  H05K2201/10674 ,  H05K2203/1469 ,  H01L2224/81 ,  H01L2924/00015 ,  H01L2224/85 ,  H01L2224/82 ,  H01L2224/45 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/48

摘要： A wiring substrate in which a semiconductor element is built includes a semiconductor element; a peripheral insulating layer covering at least an outer circumferential side surface of this semiconductor element; and an upper surface-side wiring line provided on the upper surface side of the wiring substrate. The semiconductor element includes an internal terminal electrically connected to the upper surface-side wiring line on the upper surface side of the semiconductor element. This internal terminal includes a first conductive part exposed out of an insulating surface layer of the semiconductor element; an adhesion layer on this first conductive part; and a second conductive part on this adhesion layer. The adhesion layer covers an exposed surface of the first conductive part, and is formed on a portion of the insulating surface layer around the exposed surface of the first conductive part, and the adhesion layer extends around the outer side of an outer edge of this second conductive part so as to surround the second conductive part.

摘要翻译： 构成半导体元件的布线基板包括半导体元件; 覆盖该半导体元件的至少外周侧表面的外围绝缘层; 以及设置在布线基板的上表面侧的上表面侧布线。 半导体元件包括电连接到半导体元件的上表面侧的上表面侧布线的内部端子。 该内部端子包括从半导体元件的绝缘表面层露出的第一导电部件; 在该第一导电部分上的粘附层; 和该粘合层上的第二导电部分。 粘合层覆盖第一导电部分的暴露表面，并且形成在第一导电部分的暴露表面周围的绝缘表面层的一部分上，并且粘合层围绕该第二导电部分的外边缘的外侧延伸 导电部件以包围第二导电部件。

公开(公告)号：US20130009325A1

公开(公告)日：2013-01-10

申请号：US13635621

申请日：2011-01-25

申请人： Kentaro Mori ,  Shintaro Yamamichi ,  Hideya Murai ,  Katsumi Kikuchi ,  Yoshiki Nakashima ,  Daisuke Ohshima

发明人： Kentaro Mori ,  Shintaro Yamamichi ,  Hideya Murai ,  Katsumi Kikuchi ,  Yoshiki Nakashima ,  Daisuke Ohshima

IPC分类号： H01L23/48 ,  H01L21/56 ,  H01L21/768

CPC分类号： H05K1/185 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/25 ,  H01L24/82 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/16225 ,  H01L2224/18 ,  H01L2224/2518 ,  H01L2224/32225 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/3511 ,  H05K1/187 ,  H05K3/4602 ,  H05K2201/10674 ,  H05K2203/1469 ,  H01L2924/00

摘要： A semiconductor element-embedded substrate includes a semiconductor element; a chip component; a peripheral insulating layer covering at least the outer circumferential side surfaces thereof; an upper surface-side wiring line provided on the upper surface side of the substrate; and a lower surface-side wiring line provided on the lower surface side of the substrate. The built-in semiconductor element includes a terminal on the upper surface side thereof, and this terminal is electrically connected to the upper surface-side wiring line. The built-in chip component includes an upper surface-side terminal electrically connected to the upper surface-side wiring line; a lower surface-side terminal electrically connected to the lower surface-side wiring line;and a through-chip via penetrating through the chip component to connect the upper surface-side terminal and the lower surface-side terminal.

摘要翻译： 半导体元件嵌入式基板包括半导体元件; 芯片组件; 外周绝缘层，至少覆盖其外周侧面; 设置在基板的上表面侧的上表面侧配线; 以及设置在基板的下表面侧的下表面侧配线。 内置半导体元件包括在其上表面侧的端子，该端子与上表面侧布线电连接。 内置的芯片部件包括电连接到上表面侧布线的上表面侧端子; 电连接到下表面侧布线的下表面侧端子; 以及穿过芯片部件的贯通芯片，以连接上表面侧端子和下表面侧端子。

公开(公告)号：US08304915B2

公开(公告)日：2012-11-06

申请号：US13055372

申请日：2009-07-23

申请人： Kentaro Mori ,  Hideya Murai ,  Shintaro Yamamichi ,  Masaya Kawano ,  Koji Soejima

发明人： Kentaro Mori ,  Hideya Murai ,  Shintaro Yamamichi ,  Masaya Kawano ,  Koji Soejima

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H05K1/185 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/3511 ,  H05K1/115 ,  H05K3/4644 ,  H05K2201/0352 ,  H05K2201/10674 ,  H05K2203/0152 ,  H05K2203/0156 ,  H05K2203/063 ,  H05K2203/1469 ,  H01L2924/00

摘要： A semiconductor device includes a plural number of interconnects and a plural number of vias are stacked. A semiconductor element is enclosed in an insulation layer. At least one of the vias provided in insulation layers and/or at least one of interconnects provided in the interconnect layers are of cross-sectional shapes different from those of the vias formed in another one of the insulation layers and/or interconnects provided in another one of the interconnect layers.

摘要翻译： 半导体器件包括多个互连件，并且堆叠多个通孔。 半导体元件封装在绝缘层中。 提供在绝缘层中的至少一个通孔和/或设置在互连层中的至少一个互连件的横截面形状与在另一个绝缘层中提供的另一个绝缘层和/或互连中形成的通孔的截面形状不同 互连层之一。

公开(公告)号：US08282853B2

公开(公告)日：2012-10-09

申请号：US12564483

申请日：2009-09-22

申请人： Kentaro Mori ,  Takuya Aoki

发明人： Kentaro Mori ,  Takuya Aoki

IPC分类号： H01F1/34

CPC分类号： H01F1/344 ,  C04B35/265 ,  C04B35/62685 ,  C04B2235/3208 ,  C04B2235/3244 ,  C04B2235/3251 ,  C04B2235/3263 ,  C04B2235/3279 ,  C04B2235/3284 ,  C04B2235/3418 ,  C04B2235/656 ,  C04B2235/77 ,  C04B2235/786 ,  H01F1/36 ,  H01F41/0246

摘要： A novel NiMnZn-based ferrite which can reduce magnetic loss (core loss) at a high frequency of about 2 MHz or higher and achieve higher saturated magnetic flux density while forming high sintered density is provided. The NiMnZn-based ferrite contains a main component comprising 54.0 to 57.5 mol % of iron oxide in terms of Fe2O3, 2.0 to 7.0 mol % of zinc oxide in terms of ZnO, 0.5 to 4.7 mol % of nickel oxide in terms of NiO, and a remainder of manganese oxide (in terms of MnO); and an accessory component comprising 100 to 1000 ppm by weight of Si in terms of SiO2, 800 to 3000 ppm by weight of Ca in terms of CaCO3, and 520 to 1000 ppm by weight of Nb in terms of Nb2O5 with respect to the main component; while having an average ferrite crystal particle size of 2.1 to 8.5 μm.

摘要翻译： 提供了一种新型的基于NiMnZn的铁氧体，其可以在形成高烧结密度的同时，在大约2MHz或更高的高频下降低磁损耗（磁芯损耗）并获得更高的饱和磁通密度。 NiMnZn系铁氧体含有以Fe2O3为54.0〜57.5摩尔％的氧化铁，以ZnO为2.0〜7.0摩尔％的氧化锌，NiO为0.5〜4.7摩尔％的氧化镍的主成分，以及 剩余的氧化锰（以MnO计）; 以及以SiO 2为100〜1000ppm的Si，以CaCO 3计为800〜3000质量ppm的Ca，相对于主成分为Nb 2 O 5的Nb为520〜1000质量ppm的Nb ; 而平均铁素体晶粒度为2.1〜8.5μm。

公开(公告)号：US20100078587A1

公开(公告)日：2010-04-01

申请号：US12564483

申请日：2009-09-22

申请人： Kentaro Mori ,  Takuya Aoki

发明人： Kentaro Mori ,  Takuya Aoki

IPC分类号： H01F1/01

CPC分类号： H01F1/344 ,  C04B35/265 ,  C04B35/62685 ,  C04B2235/3208 ,  C04B2235/3244 ,  C04B2235/3251 ,  C04B2235/3263 ,  C04B2235/3279 ,  C04B2235/3284 ,  C04B2235/3418 ,  C04B2235/656 ,  C04B2235/77 ,  C04B2235/786 ,  H01F1/36 ,  H01F41/0246

摘要： A novel NiMnZn-based ferrite which can reduce magnetic loss (core loss) at a high frequency of about 2 MHz or higher and achieve higher saturated magnetic flux density while forming high sintered density is provided. The NiMnZn-based ferrite contains a main component comprising 54.0 to 57.5 mol % of iron oxide in terms of Fe2O3, 2.0 to 7.0 mol % of zinc oxide in terms of ZnO, 0.5 to 4.7 mol % of nickel oxide in terms of NiO, and a remainder of manganese oxide (in terms of MnO); and an accessory component comprising 100 to 1000 ppm by weight of Si in terms of SiO2, 800 to 3000 ppm by weight of Ca in terms of CaCO3, and 520 to 1000 ppm by weight of Nb in terms of Nb2O5 with respect to the main component; while having an average ferrite crystal particle size of 2.1 to 8.5 μm.

摘要翻译： 提供了一种新型的基于NiMnZn的铁氧体，其可以在形成高烧结密度的同时，在大约2MHz或更高的高频下降低磁损耗（磁芯损耗）并获得更高的饱和磁通密度。 NiMnZn系铁氧体含有以Fe2O3为54.0〜57.5摩尔％的氧化铁，以ZnO为2.0〜7.0摩尔％的氧化锌，NiO为0.5〜4.7摩尔％的氧化镍的主成分，以及 剩余的氧化锰（以MnO计）; 以及以SiO 2为100〜1000ppm的Si，以CaCO 3计为800〜3000质量ppm的Ca，相对于主成分为Nb 2 O 5的Nb为520〜1000质量ppm的Nb ; 而平均铁素体晶粒度为2.1〜8.5μm。

公开(公告)号：US20090315190A1

公开(公告)日：2009-12-24

申请号：US12306987

申请日：2007-06-29

申请人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Hideya Murai ,  Takuo Funaya ,  Kentaro Mori ,  Takehiko Maeda ,  Hirokazu Honda ,  Kenta Ogawa ,  Jun Tsukano

发明人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Hideya Murai ,  Takuo Funaya ,  Kentaro Mori ,  Takehiko Maeda ,  Hirokazu Honda ,  Kenta Ogawa ,  Jun Tsukano

IPC分类号： H01L23/538 ,  H05K1/11 ,  H01L21/60 ,  H01L21/31

CPC分类号： H05K3/205 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/563 ,  H01L23/498 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48472 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/181 ,  H01L2924/19041 ,  H05K3/244 ,  H05K3/423 ,  H05K2201/0338 ,  H05K2201/098 ,  H05K2201/09845 ,  H05K2203/0376 ,  H05K2203/0384 ,  H05K2203/0733 ,  H05K2203/1476 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/45015 ,  H01L2924/207

摘要： A wiring board has an insulating layer, a plurality of wiring layers formed in such a way as to be insulated from each other by the insulating layer, and a plurality of vias formed in the insulating layer to connect the wiring layers. Of the wiring layers, a surface wiring layer formed in one surface of the insulating layer include a first metal film exposed from the one surface and a second metal film embedded in the insulating layer and stacked on the first metal film. Edges of the first metal film project from edges of the second metal film in the direction in which the second metal film spreads. By designing the shape of the wiring layers embedded in the insulating layer in this manner, it is possible to obtain a highly reliable wiring board that can be effectively prevented from side etching in the manufacturing process and can adapt to miniaturization and highly dense packaging of wires.

摘要翻译： 布线基板具有绝缘层，多个布线层以通过绝缘层彼此绝缘的方式形成，以及形成在绝缘层中以连接布线层的多个通孔。 在布线层中，形成在绝缘层的一个表面上的表面布线层包括从一个表面露出的第一金属膜和嵌入在绝缘层中并叠放在第一金属膜上的第二金属膜。 第一金属膜的边缘沿着第二金属膜扩展的方向从第二金属膜的边缘突出。 通过以这种方式设计嵌入在绝缘层中的布线层的形状，可以获得在制造过程中可以有效地防止侧蚀刻的高可靠性布线板，并且可以适应电线的小型化和高密度封装 。

公开(公告)号：US20080303136A1

公开(公告)日：2008-12-11

申请号：US12135355

申请日：2008-06-09

申请人： Kentaro Mori ,  Shintaro Yamamichi ,  Hideya Murai ,  Takuo Funaya ,  Masaya Kawano ,  Takehiko Maeda ,  Kouji Soejima

发明人： Kentaro Mori ,  Shintaro Yamamichi ,  Hideya Murai ,  Takuo Funaya ,  Masaya Kawano ,  Takehiko Maeda ,  Kouji Soejima

IPC分类号： H01L23/15 ,  H01L21/58

CPC分类号： H01L21/6835 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/19 ,  H01L24/24 ,  H01L2221/68345 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2223/54486 ,  H01L2224/04105 ,  H01L2224/24226 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/15174 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/3011 ,  Y10S438/977 ,  H01L2924/00

摘要： A transparent board is positioned on a support board provided with a positioning mark, and a release material is provided. A semiconductor element is then positioned so that the electrode element faces upward, and the support board is then removed. An insulating resin is then formed on the release material so as to cover the semiconductor element; and a via, a wiring layer, an insulation layer, an external terminal, and a solder resist are then formed. The transparent board is then peeled from the semiconductor device through the use of the release material. A chip can thereby be mounted with high precision, there is no need to provide a positioning mark during mounting of the chip on the substrate in the manufacturing process, and the substrate can easily be removed. As a result, a semiconductor device having high density and a thin profile can be manufactured at low cost.

摘要翻译： 透明板位于设置有定位标记的支撑板上，并且设置有释放材料。 然后将半导体元件定位成使得电极元件面向上，然后移除支撑板。 然后在剥离材料上形成绝缘树脂以覆盖半导体元件; 然后形成通孔，布线层，绝缘层，外部端子和阻焊剂。 然后透明板通过使用释放材料从半导体器件剥离。 因此，可以高精度地安装芯片，在制造过程中不需要在将芯片安装在基板上时提供定位标记，并且可以容易地去除基板。 结果，可以以低成本制造具有高密度和薄型的半导体器件。

公开(公告)号：US06379310B1

公开(公告)日：2002-04-30

申请号：US09582985

申请日：2000-07-10

申请人： Kentaro Mori ,  Takahide Tanaka ,  Akira Nakagawa ,  Iwao Kojima

发明人： Kentaro Mori ,  Takahide Tanaka ,  Akira Nakagawa ,  Iwao Kojima

IPC分类号： A61B502

CPC分类号： A61B5/681 ,  A61B5/02141 ,  A61B5/0225 ,  A61B5/742 ,  A61B2560/0406 ,  A61B2560/0443

摘要： A sphygmomanometer includes a body 10 and a cuff 20 which is integrally attached to the body 10 and wrapped around the wrist. The body 10 is attached to the cuff 20 such that the body is located on the thumb side of the arm L when the sphygmomanometer is fitted on the wrist. Consequently, a precise blood pressure measurement and precise blood pressure fluctuation can be obtained without restriction on the location where the blood pressure measurement is conducted.

摘要翻译： 血压计包括主体10和袖带20，其整体地附接到主体10并缠绕在手腕上。 主体10附接到袖带20，使得当血压计安装在手腕上时，身体位于臂L的拇指侧。 因此，可以在不受限制进行血压测量的位置的情况下获得精确的血压测量和精确的血压波动。